IT1115359B - Dispositivo di sincronizzazione di un ricevitore in un sistema di trasmissione di dati - Google Patents

Dispositivo di sincronizzazione di un ricevitore in un sistema di trasmissione di dati

Info

Publication number
IT1115359B
IT1115359B IT24961/77A IT2496177A IT1115359B IT 1115359 B IT1115359 B IT 1115359B IT 24961/77 A IT24961/77 A IT 24961/77A IT 2496177 A IT2496177 A IT 2496177A IT 1115359 B IT1115359 B IT 1115359B
Authority
IT
Italy
Prior art keywords
receiver
data transmission
transmission system
synchronization device
synchronization
Prior art date
Application number
IT24961/77A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1115359B publication Critical patent/IT1115359B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)
IT24961/77A 1976-07-09 1977-06-23 Dispositivo di sincronizzazione di un ricevitore in un sistema di trasmissione di dati IT1115359B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7621564A FR2358056A1 (fr) 1976-07-09 1976-07-09 Procede et dispositif de synchronisation de l'horloge du recepteur d'un systeme de transmissions de donnees en modulation psk

Publications (1)

Publication Number Publication Date
IT1115359B true IT1115359B (it) 1986-02-03

Family

ID=9175724

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24961/77A IT1115359B (it) 1976-07-09 1977-06-23 Dispositivo di sincronizzazione di un ricevitore in un sistema di trasmissione di dati

Country Status (10)

Country Link
US (1) US4137427A (it)
JP (1) JPS538507A (it)
AU (1) AU510474B2 (it)
CH (1) CH624518A5 (it)
DE (1) DE2729312C2 (it)
ES (1) ES460526A1 (it)
FR (1) FR2358056A1 (it)
GB (1) GB1540510A (it)
IT (1) IT1115359B (it)
SE (1) SE435439B (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2319915B (en) * 1996-11-29 2001-01-24 Lsi Logic Corp Analogue to digital converter system
GB2026796B (en) * 1978-07-14 1982-09-29 Fujitsu Ltd Clock synchronization circuit
FR2441298A1 (fr) * 1978-11-07 1980-06-06 Cit Alcatel Dispositif de recuperation de rythme
DE2950339C2 (de) * 1979-12-14 1984-06-07 ANT Nachrichtentechnik GmbH, 7150 Backnang Verfahren und Anordnung zur digitalen Regelung der Trägerphase in Empfängern von Datenübertragungssystemen
DE3027053A1 (de) * 1980-07-17 1982-02-11 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur zeitlichen korrektur von digitalen schaltsignalen
DE3037778A1 (de) * 1980-10-07 1982-05-19 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur zeitlichen korrektur von digitalen schaltsignalen
DE3047806A1 (de) * 1980-12-18 1982-07-15 Siemens AG, 1000 Berlin und 8000 München Verfahren zur regelung des empfangstaktes bei der datenuebertragung mittels phasenmodulation
US4455663A (en) * 1981-11-19 1984-06-19 Novation, Inc. Full duplex modems and synchronizing methods and apparatus therefor
JPS5980309U (ja) * 1982-11-24 1984-05-30 三山工機株式会社 コンベアベルト
DE3227151C2 (de) * 1982-07-21 1986-04-17 Standard Elektrik Lorenz Ag, 7000 Stuttgart Einrichtung zur empfangsseitigen Phasensynchronisation des Abtasttaktes auf die Phasenlage der Zeichen eines empfangenen Zeitmultiplex-Zeichenstroms
GB2153186B (en) * 1984-01-13 1987-04-23 Ncr Co Digital data receiver including timing adjustment circuit
FR2604318B1 (fr) * 1986-09-23 1989-03-31 Thomson Csf Procede et dispositif de synchronisation symbole et leur application a la demodulation symbole de messages numeriques
CA1311033C (en) * 1988-03-19 1992-12-01 Shinji Ohta Circuit for obtaining accurate timing information received signal
JP2884792B2 (ja) * 1991-02-19 1999-04-19 日本電気株式会社 タイミング抽出装置
DE69737171T2 (de) * 1996-07-22 2007-10-04 Nippon Telegraph And Telephone Corp. Schaltung zur Taktrückgewinnung
DE19825070C1 (de) * 1998-06-04 2000-01-05 Ericsson Telefon Ab L M Verfahren zur Bestimmung eines eine Variation zwischen einer meßbaren Größe und einer meßbaren Referenzgröße repräsentierenden Wertes
DE19956947A1 (de) * 1999-11-26 2001-05-31 Philips Corp Intellectual Pty Anordnung zur Feststellung der Phasenlage eines Datensignals
FR2822323B1 (fr) * 2001-03-15 2003-12-19 Cit Alcatel Procede de recuperation de rythme de paquets de signaux numeriques
DE10203596C1 (de) * 2002-01-30 2003-08-14 Infineon Technologies Ag Verfahren zur Abtastphasenregelung
WO2005022855A1 (en) * 2003-08-29 2005-03-10 Bandwidth Foundry Pty Ltd A clock signal distribution network and method
US7362840B2 (en) * 2004-11-18 2008-04-22 Freescale Semiconductor Inc. Circuit and method for adjusting timing alignment using programmable codes
TWI556584B (zh) * 2015-03-26 2016-11-01 威盛電子股份有限公司 相位偵測裝置以及相位調整方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2164544B1 (it) * 1971-12-21 1974-09-27 Ibm France
FR2309089A1 (fr) * 1975-04-25 1976-11-19 Ibm France Procede pour synchroniser l'horloge du recepteur d'un systeme de transmission de donnees et dispositif pour mettre en oeuvre le procede

Also Published As

Publication number Publication date
DE2729312C2 (de) 1983-04-07
AU2830077A (en) 1979-03-08
FR2358056B1 (it) 1978-12-15
SE7707932L (sv) 1978-01-10
SE435439B (sv) 1984-09-24
US4137427A (en) 1979-01-30
CH624518A5 (it) 1981-07-31
GB1540510A (en) 1979-02-14
ES460526A1 (es) 1978-12-01
JPS5753018B2 (it) 1982-11-10
DE2729312A1 (de) 1978-01-19
FR2358056A1 (fr) 1978-02-03
JPS538507A (en) 1978-01-26
AU510474B2 (en) 1980-06-26

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