IN2015MN00051A - - Google Patents

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Publication number
IN2015MN00051A
IN2015MN00051A IN51MUN2015A IN2015MN00051A IN 2015MN00051 A IN2015MN00051 A IN 2015MN00051A IN 51MUN2015 A IN51MUN2015 A IN 51MUN2015A IN 2015MN00051 A IN2015MN00051 A IN 2015MN00051A
Authority
IN
India
Prior art keywords
memory
physical
addresses
stage
translation
Prior art date
Application number
Other languages
English (en)
Inventor
Sudeep Ravi Kottilingal
Ramesh Ramaswamy
Suhail Jalil
Azzedine Touzni
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2015MN00051A publication Critical patent/IN2015MN00051A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/151—Emulated environment, e.g. virtual machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/651—Multi-level translation tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Information Transfer Between Computers (AREA)
IN51MUN2015 2012-08-07 2013-06-13 IN2015MN00051A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/568,523 US9047090B2 (en) 2012-08-07 2012-08-07 Methods, systems and devices for hybrid memory management
PCT/US2013/045685 WO2014025454A1 (en) 2012-08-07 2013-06-13 Methods, systems and devices for hybrid memory management

Publications (1)

Publication Number Publication Date
IN2015MN00051A true IN2015MN00051A (pt) 2015-10-16

Family

ID=48747725

Family Applications (1)

Application Number Title Priority Date Filing Date
IN51MUN2015 IN2015MN00051A (pt) 2012-08-07 2013-06-13

Country Status (6)

Country Link
US (1) US9047090B2 (pt)
EP (1) EP2883146A1 (pt)
JP (1) JP5916955B2 (pt)
CN (1) CN104520823B (pt)
IN (1) IN2015MN00051A (pt)
WO (1) WO2014025454A1 (pt)

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US9547361B2 (en) * 2015-04-29 2017-01-17 Qualcomm Incorporated Methods and apparatuses for memory power reduction
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JP6212073B2 (ja) * 2015-06-29 2017-10-11 ファナック株式会社 プログラムの内容に応じて格納先を自動選択する機能を備えた数値制御装置
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US20170262367A1 (en) * 2016-03-11 2017-09-14 Qualcomm Incorporated Multi-rank collision reduction in a hybrid parallel-serial memory system
CN106657718B (zh) * 2016-11-07 2019-12-06 金陵科技学院 实现虚拟现实的数据传送系统及其方法
US10866912B2 (en) 2017-03-10 2020-12-15 Toshiba Memory Corporation Integrated heterogeneous solid state storage drive
CN107102824B (zh) * 2017-05-26 2019-08-30 华中科技大学 一种基于存储和加速优化的Hadoop异构方法和系统
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US10445009B2 (en) * 2017-06-30 2019-10-15 Intel Corporation Systems and methods of controlling memory footprint
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CN110265029A (zh) * 2019-06-21 2019-09-20 百度在线网络技术（北京）有限公司 语音芯片和电子设备
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Also Published As

Publication number Publication date
US20140047251A1 (en) 2014-02-13
JP2015528597A (ja) 2015-09-28
US9047090B2 (en) 2015-06-02
JP5916955B2 (ja) 2016-05-11
EP2883146A1 (en) 2015-06-17
CN104520823B (zh) 2016-05-04
WO2014025454A1 (en) 2014-02-13
CN104520823A (zh) 2015-04-15

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