IN2014MN02115A - - Google Patents
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- Publication number
- IN2014MN02115A IN2014MN02115A IN2115MUN2014A IN2014MN02115A IN 2014MN02115 A IN2014MN02115 A IN 2014MN02115A IN 2115MUN2014 A IN2115MUN2014 A IN 2115MUN2014A IN 2014MN02115 A IN2014MN02115 A IN 2014MN02115A
- Authority
- IN
- India
- Prior art keywords
- memory
- die
- logic die
- clock signal
- clock
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H10W90/00—
-
- H10W70/60—
-
- H10W74/00—
-
- H10W90/722—
-
- H10W90/724—
-
- H10W90/754—
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261654156P | 2012-06-01 | 2012-06-01 | |
| US13/752,427 US9448947B2 (en) | 2012-06-01 | 2013-01-29 | Inter-chip memory interface structure |
| PCT/US2013/043714 WO2013181603A2 (en) | 2012-06-01 | 2013-05-31 | Inter-chip memory interface structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2014MN02115A true IN2014MN02115A (th) | 2015-09-11 |
Family
ID=49671774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN2115MUN2014 IN2014MN02115A (th) | 2012-06-01 | 2013-05-31 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9448947B2 (th) |
| EP (1) | EP2856466B1 (th) |
| JP (1) | JP6105720B2 (th) |
| KR (1) | KR101748329B1 (th) |
| CN (1) | CN104335279B (th) |
| IN (1) | IN2014MN02115A (th) |
| WO (1) | WO2013181603A2 (th) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102107147B1 (ko) * | 2013-02-01 | 2020-05-26 | 삼성전자주식회사 | 패키지 온 패키지 장치 |
| KR102144367B1 (ko) * | 2013-10-22 | 2020-08-14 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| US9570142B2 (en) * | 2015-05-18 | 2017-02-14 | Micron Technology, Inc. | Apparatus having dice to perorm refresh operations |
| US20170118140A1 (en) * | 2015-10-21 | 2017-04-27 | Mediatek Inc. | Network switch having identical dies and interconnection network packaged in same package |
| KR102755934B1 (ko) | 2016-10-04 | 2025-01-17 | 삼성전자 주식회사 | 무선 통신 장치 및 그 제어 방법 |
| KR102400101B1 (ko) | 2017-11-03 | 2022-05-19 | 삼성전자주식회사 | Pop 반도체 패키지 및 그를 포함하는 전자 시스템 |
| US10579557B2 (en) * | 2018-01-16 | 2020-03-03 | Advanced Micro Devices, Inc. | Near-memory hardened compute blocks for configurable computing substrates |
| KR20190087893A (ko) * | 2018-01-17 | 2019-07-25 | 삼성전자주식회사 | 클럭을 공유하는 반도체 패키지 및 전자 시스템 |
| KR102674550B1 (ko) | 2019-10-07 | 2024-06-13 | 삼성전자주식회사 | 온-다이 미러링 기능을 갖는 메모리 칩 및 그것을 테스트하는 방법 |
| US11797229B2 (en) * | 2020-07-02 | 2023-10-24 | Micron Technology, Inc. | Multiple register clock driver loaded memory subsystem |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945886A (en) * | 1996-09-20 | 1999-08-31 | Sldram, Inc. | High-speed bus structure for printed circuit boards |
| US7352602B2 (en) * | 2005-12-30 | 2008-04-01 | Micron Technology, Inc. | Configurable inputs and outputs for memory stacking system and method |
| JP2008140220A (ja) | 2006-12-04 | 2008-06-19 | Nec Corp | 半導体装置 |
| US8120958B2 (en) * | 2007-12-24 | 2012-02-21 | Qimonda Ag | Multi-die memory, apparatus and multi-die memory stack |
| US7701251B1 (en) | 2008-03-06 | 2010-04-20 | Xilinx, Inc. | Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package |
| US7944726B2 (en) | 2008-09-30 | 2011-05-17 | Intel Corporation | Low power termination for memory modules |
| US20100174858A1 (en) | 2009-01-05 | 2010-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Extra high bandwidth memory die stack |
| US8683164B2 (en) * | 2009-02-04 | 2014-03-25 | Micron Technology, Inc. | Stacked-die memory systems and methods for training stacked-die memory systems |
| US8713248B2 (en) * | 2009-06-02 | 2014-04-29 | Nokia Corporation | Memory device and method for dynamic random access memory having serial interface and integral instruction buffer |
| US8296526B2 (en) * | 2009-06-17 | 2012-10-23 | Mediatek, Inc. | Shared memory having multiple access configurations |
| US8604593B2 (en) * | 2009-10-19 | 2013-12-10 | Mosaid Technologies Incorporated | Reconfiguring through silicon vias in stacked multi-die packages |
| US8472279B2 (en) * | 2010-08-31 | 2013-06-25 | Micron Technology, Inc. | Channel skewing |
| US20120137090A1 (en) * | 2010-11-29 | 2012-05-31 | Sukalpa Biswas | Programmable Interleave Select in Memory Controller |
| US8400808B2 (en) * | 2010-12-16 | 2013-03-19 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
| JP2013058277A (ja) * | 2011-09-07 | 2013-03-28 | Renesas Electronics Corp | 半導体装置 |
| US20130159587A1 (en) * | 2011-12-15 | 2013-06-20 | Aaron Nygren | Interconnect Redundancy for Multi-Interconnect Device |
-
2013
- 2013-01-29 US US13/752,427 patent/US9448947B2/en active Active
- 2013-05-31 JP JP2015515261A patent/JP6105720B2/ja active Active
- 2013-05-31 EP EP13729562.2A patent/EP2856466B1/en active Active
- 2013-05-31 IN IN2115MUN2014 patent/IN2014MN02115A/en unknown
- 2013-05-31 WO PCT/US2013/043714 patent/WO2013181603A2/en not_active Ceased
- 2013-05-31 CN CN201380028442.0A patent/CN104335279B/zh active Active
- 2013-05-31 KR KR1020147036817A patent/KR101748329B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US9448947B2 (en) | 2016-09-20 |
| JP6105720B2 (ja) | 2017-03-29 |
| WO2013181603A2 (en) | 2013-12-05 |
| KR20150016605A (ko) | 2015-02-12 |
| US20130326188A1 (en) | 2013-12-05 |
| EP2856466A2 (en) | 2015-04-08 |
| WO2013181603A3 (en) | 2014-02-27 |
| KR101748329B1 (ko) | 2017-06-16 |
| EP2856466B1 (en) | 2018-10-24 |
| CN104335279B (zh) | 2017-08-15 |
| CN104335279A (zh) | 2015-02-04 |
| JP2015525398A (ja) | 2015-09-03 |
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