IN2014CN02249A - - Google Patents

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Publication number
IN2014CN02249A
IN2014CN02249A IN2249CHN2014A IN2014CN02249A IN 2014CN02249 A IN2014CN02249 A IN 2014CN02249A IN 2249CHN2014 A IN2249CHN2014 A IN 2249CHN2014A IN 2014CN02249 A IN2014CN02249 A IN 2014CN02249A
Authority
IN
India
Prior art keywords
different
nvr
coupling links
lines
memory
Prior art date
Application number
Inventor
Jung Pill Kim
Taehyun Kim
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN02249A publication Critical patent/IN2014CN02249A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Abstract

A memory has a plurality of non volatile resistive (NVR) memory arrays each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally different ones of the reference coupling links are removed or opened obtaining respective different average and isolated reference voltages on the different reference lines. Optionally different ones of the reference circuit coupling links are removed or opened obtaining respective different averaged voltages on the reference lines and uncoupling and isolating different reference circuits.
IN2249CHN2014 2011-10-21 2012-10-22 IN2014CN02249A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/278,217 US8675390B2 (en) 2011-10-21 2011-10-21 System and method for MRAM having controlled averagable and isolatable voltage reference
PCT/US2012/061359 WO2013059808A1 (en) 2011-10-21 2012-10-22 System and method for mram having controlled averagable and isolatable voltage reference

Publications (1)

Publication Number Publication Date
IN2014CN02249A true IN2014CN02249A (en) 2015-06-12

Family

ID=47146707

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2249CHN2014 IN2014CN02249A (en) 2011-10-21 2012-10-22

Country Status (7)

Country Link
US (3) US8675390B2 (en)
EP (1) EP2769381B1 (en)
JP (1) JP6054976B2 (en)
KR (1) KR101639343B1 (en)
CN (1) CN103890849B (en)
IN (1) IN2014CN02249A (en)
WO (1) WO2013059808A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8675390B2 (en) 2011-10-21 2014-03-18 Qualcomm Incorporated System and method for MRAM having controlled averagable and isolatable voltage reference
EP2831881A4 (en) * 2012-03-29 2016-04-20 Intel Corp Magnetic state element and circuits
JP2016151183A (en) * 2015-02-16 2016-08-22 いすゞ自動車株式会社 Exhaust emission control system for internal combustion engine, internal combustion engine and exhaust emission control method
US10032509B2 (en) * 2015-03-30 2018-07-24 Toshiba Memory Corporation Semiconductor memory device including variable resistance element
US9444406B1 (en) * 2015-06-29 2016-09-13 Silicon Laboratories Inc. Amplifier topology achieving high DC gain and wide output voltage range
US9947380B2 (en) * 2016-03-11 2018-04-17 Toshiba Memory Corporation Adjustable read reference voltage to reduce errors in memory devices
CN111163245B (en) * 2018-11-08 2021-11-23 杭州海康威视数字技术股份有限公司 Method and device for adding network camera in network hard disk video recorder
CN110060713B (en) * 2019-04-28 2021-10-22 中国科学院微电子研究所 Reading time sequence generation device with process floating tolerance

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3661470B2 (en) 1999-02-15 2005-06-15 フジノン株式会社 Tissue collection device
JP2001177065A (en) * 1999-12-17 2001-06-29 Hitachi Ltd Semiconductor integrated circuit device and method of switching internal voltage
US6317376B1 (en) 2000-06-20 2001-11-13 Hewlett-Packard Company Reference signal generation for magnetic random access memory devices
US6434044B1 (en) * 2001-02-16 2002-08-13 Sandisk Corporation Method and system for generation and distribution of supply voltages in memory systems
JP3821066B2 (en) 2002-07-04 2006-09-13 日本電気株式会社 Magnetic random access memory
JP4195266B2 (en) * 2002-09-13 2008-12-10 スパンション エルエルシー Semiconductor memory device
US6801448B2 (en) 2002-11-26 2004-10-05 Sharp Laboratories Of America, Inc. Common bit/common source line high density 1T1R R-RAM array
KR100492781B1 (en) * 2003-05-23 2005-06-07 주식회사 하이닉스반도체 Non-volatile ferroelectric memory device for controlling multi-bit
US7016249B2 (en) * 2003-06-30 2006-03-21 Intel Corporation Reference voltage generator
JP2005050421A (en) * 2003-07-28 2005-02-24 Sharp Corp Semiconductor storage device
JP4192060B2 (en) * 2003-09-12 2008-12-03 シャープ株式会社 Nonvolatile semiconductor memory device
JP4200872B2 (en) * 2003-10-15 2008-12-24 沖電気工業株式会社 Semiconductor integrated circuit
US7075817B2 (en) * 2004-07-20 2006-07-11 Unity Semiconductor Corporation Two terminal memory array having reference cells
KR100604913B1 (en) 2004-10-28 2006-07-28 삼성전자주식회사 Magnetoresistive RAM having multi-bit cell array configuration
JP4993118B2 (en) 2005-02-08 2012-08-08 日本電気株式会社 Semiconductor memory device and method for reading semiconductor memory device
JP4890016B2 (en) * 2005-03-16 2012-03-07 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
KR100735750B1 (en) 2005-12-15 2007-07-06 삼성전자주식회사 Semiconductor devices including a reference cell block and sense amplification units for generating a plurality of uniform reference data and systems employing the same
US8134866B2 (en) * 2006-04-06 2012-03-13 Samsung Electronics Co., Ltd. Phase change memory devices and systems, and related programming methods
US7382644B2 (en) * 2006-06-29 2008-06-03 Unity Semiconductor Corporation Two terminal memory array having reference cells
US8139432B2 (en) * 2006-12-27 2012-03-20 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
JP2009117003A (en) 2007-11-09 2009-05-28 Toshiba Corp Data reading method for nonvolatile memory device
US8027192B2 (en) 2008-08-20 2011-09-27 Samsung Electronics Co., Ltd. Resistive memory devices using assymetrical bitline charging and discharging
JP2010079974A (en) 2008-09-25 2010-04-08 Toshiba Corp Semiconductor memory device
JP2010182353A (en) * 2009-02-04 2010-08-19 Elpida Memory Inc Semiconductor memory device and reading method therefor
US8395925B2 (en) * 2009-06-08 2013-03-12 Panasonic Corporation Forming method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device
JP5214566B2 (en) * 2009-09-02 2013-06-19 株式会社東芝 Resistance change memory device
US8724414B2 (en) * 2010-02-09 2014-05-13 Qualcomm Incorporated System and method to select a reference cell
US8587994B2 (en) * 2010-09-08 2013-11-19 Qualcomm Incorporated System and method for shared sensing MRAM
JP2012069181A (en) * 2010-09-21 2012-04-05 Toshiba Corp Semiconductor storage device
JP5803480B2 (en) * 2011-09-20 2015-11-04 株式会社ソシオネクスト Semiconductor memory device and data reading method
US8675390B2 (en) 2011-10-21 2014-03-18 Qualcomm Incorporated System and method for MRAM having controlled averagable and isolatable voltage reference

Also Published As

Publication number Publication date
EP2769381A1 (en) 2014-08-27
JP2014531104A (en) 2014-11-20
US20160358649A1 (en) 2016-12-08
CN103890849A (en) 2014-06-25
US9455031B2 (en) 2016-09-27
CN103890849B (en) 2017-03-01
US9666274B2 (en) 2017-05-30
KR101639343B1 (en) 2016-07-22
JP6054976B2 (en) 2016-12-27
US8675390B2 (en) 2014-03-18
US20140133216A1 (en) 2014-05-15
WO2013059808A1 (en) 2013-04-25
KR20140093687A (en) 2014-07-28
EP2769381B1 (en) 2019-09-25
US20130100725A1 (en) 2013-04-25

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