JP2001177065A - Semiconductor integrated circuit device and method of switching internal voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly enhance the yield of manufacture, by relieving a voltage generating circuit which generates reference voltage beyond a trimming range. SOLUTION: At probe inspection, the reference voltages VREF of reference voltage circuits 11-14 and 15-18 are measured to perform the relief decision. The setting is performed so that the reference voltage VREF may come closer to the design value, by performing the trimming for only the reference voltage circuit being decided to be up to the standard, if any reference voltage circuit is decided to be short of standard among the reference voltage circuits 11-14 and 15-18. A reference voltage circuit which measures the reference voltage VREF of the trimmed reference voltage circuit and generates the reference voltage VREF which is the closet to the design value is detected. The fuses provided in reference voltage selectors 19-22 are cut to switch the destination of connection, and the reference voltage VREF generated by the reference voltage circuit is supplied to internal circuits which supply reference voltages VREF, being provided in all DRAM macros 2-5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rescue technique for a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a rescue technique for a voltage generating circuit in a semiconductor integrated circuit device constituted by a plurality of macros. .

[0002]

2. Description of the Related Art In a memory such as a DRAM, a large number of I / Os (Inpu
t / Output), a so-called logic embedded DRAM (Dynamic Random Acces)
s Memory).

[0003] This logic embedded DRAM has a plurality of DRs.
This is a semiconductor integrated circuit device including an AM macro and a logic circuit controlling these DRAM macros.

According to studies made by the present inventors, a DRAM macro provided in a logic-embedded DRAM is provided with a reference voltage generation circuit for generating a reference voltage V _REF . This is because a plurality of DRAM macros are formed by copying a pre-designed master macro cell in order to increase design efficiency.

The reference voltage V _REF generated by the reference voltage generation circuit is used, for example, as a reference voltage in a level monitor provided in a boost power supply circuit. The boost power supply circuit generates a boost power supply voltage V _{PP and the} like, and the boost power supply voltage V _PP is used as a word line potential or the like. Level monitor monitors the voltage level of the boosted power supply voltage V _PP, performs level control of the boosted power supply voltage V _PP.

An example of this type of semiconductor integrated circuit device is described in detail in November 5, 1994.
Published by Baifukan Co., Ltd., Kiyoo Ito (Author), "Advanced Electronics I-9 Ultra LSI Memory" P31
This document describes the structure of a booster power supply circuit provided in a DRAM.

[0007]

However, the inventor of the present invention has found that the above-mentioned logic-embedded DRAM has the following problems.

That is, the reference voltage generation circuit is provided with a trimming circuit for finely adjusting the generated reference voltage V _REF , but the reference voltage V out of the plurality of DRAM macros exceeds the trimming range. D to generate _REF
When there is a RAM macro, the logic-embedded DRAM itself becomes a defective product, and there is a problem that the production yield is not improved.

An object of the present invention is to provide a semiconductor integrated circuit device which can rescue a power supply circuit for generating a reference voltage exceeding a trimming range and can greatly improve a manufacturing yield.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention has a configuration in which two or more macro cells are provided, and a voltage generation circuit for generating a certain level of internal voltage is provided in each of the two or more macro cells. A selection signal generation unit for generating a selection signal, a control signal generation unit for generating first and second control signals based on the selection signal generated by the selection signal generation unit, and a control signal generation unit. First
A first switching unit that supplies an internal voltage generated by the voltage generation circuit based on the control signal to an internal circuit of the macro cell; and a first switching unit that is provided in the internal circuit based on a second control signal generated by the control signal generation unit. A second switching section for controlling connection between the internal voltage input section and the common wiring and a voltage generating circuit switching means are provided.

Further, the method of switching internal voltages according to the present invention measures internal voltages generated by voltage generating circuits respectively provided in two or more macrocells, and determines whether or not the internal voltages are within a standard value range. In the case where there is a judging step and a voltage generating circuit for generating an internal voltage out of the range of the standard value, the first and second circuits provided in the voltage generating circuit switching means provided in each of the two or more macrocells And switching the connection destination of the switching section to supply the internal voltage of the voltage generation circuit that generates the internal voltage closest to the reference value to all the internal circuits.

As described above, when there is a voltage generating circuit that generates an internal voltage that is out of specification, the voltage generating circuit switching means converts the internal voltage generated by the voltage generating circuit that generates the internal voltage closest to the reference value to the internal voltage. Since the voltage can be supplied to the internal circuits provided in the respective macro cells, a defective voltage generating circuit can be relieved, and the production yield of the semiconductor integrated circuit device can be improved.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to one embodiment of the present invention, and FIG. 2 is a control signal in a reference voltage selecting section provided in each DRAM macro according to one embodiment of the present invention. Circuit diagram of output section, FIG.
FIG. 4 is a circuit diagram of a switching circuit and a control circuit provided in a reference voltage selection unit according to one embodiment of the present invention. FIG. 4 is a diagram illustrating selection of a reference voltage circuit in the reference voltage selection unit according to one embodiment of the present invention. It is a flowchart of a switching operation.

In the present embodiment, the semiconductor integrated circuit device 1 is a logic embedded DRAM, and is composed of eight DRAM macros (macro cells) 2 to 9 and a logic circuit 10 as shown in FIG. .

The logic circuit 10 is laid out at the center of the semiconductor chip. DRAM macros 2 to 5 are laid out above the logic circuit 10 and DRAM macros 6 to 9 are laid out below.

Each of the DRAM macros 2 to 9 has a DR
This is a circuit block that functions as an AM. The logic circuit 10 includes a logic control unit that controls the semiconductor integrated circuit device 1 and a memory unit that temporarily stores input / output data. The memory unit is an SRAM (St
ati Random Access Memory)
Consists of

The DRAM macros 2 to 9 are provided with reference voltage circuits (voltage generation circuits) 11 to 18 and reference voltage selection units (voltage generation circuit switching means) 19 to 26, respectively. Each of the reference voltage circuits 11 to 18 includes a reference voltage generator and a trimming circuit that trims and outputs a reference voltage (internal voltage) V _REF generated by the reference voltage generator.

The trimming circuit cuts the fuse generated by polycrystalline silicon or the like, trims the reference voltage _VREF , and outputs the trimmed reference voltage _VREF . The reference voltage V _REF is used, for example, as a reference voltage in a level monitor provided in a boost power supply circuit.

The reference voltage generator generates a boosted power supply voltage V _PP used as a word line potential or the like, and the level monitor monitors the voltage level of the boosted power supply voltage V _PP and controls the reference voltage generator. The boosted power supply voltage V _PP at the optimum voltage level is output.

The reference voltage selection units 19 to 26 include voltage terminals.
Terminals T1 to T3 are provided, and a voltage terminal T
1 is connected to reference voltage circuits 11 to 18 respectively.
The reference voltage circuit 11 is connected via the voltage terminal T1.
-18 generated reference voltage V _REFIs entered.

The common terminal 2 is connected to the voltage terminals T2 of the reference voltage selectors 19 to 22 provided in the DRAM macros 2 to 5.
7 are connected to each other, and the voltage terminals T2 of the reference voltage selectors 23 to 26 provided in the DRAM macros 6 to 9 are connected.
Are connected to a common wiring 27, respectively. The voltage terminal T3 is connected to an internal circuit that requires the reference voltage V _REF such as a boost power supply circuit provided in the DRAM macros 2 to 9, respectively.

The circuit configuration of the reference voltage selector 19 (to 26) provided in the DRAM macro 2 (to 9) will be described.

The reference voltage selection section 19 (-26) is provided in
As shown in FIG. 3, a control signal output unit (selection signal generation unit)
It is composed of CS1 and CS2, switching circuits SW1 and SW2, and a control circuit (control signal generation unit) CT that controls the switching circuits SW1 and SW2 based on the output signals of the control signal output units CS1 and CS2.

As shown in FIG. 2, the control signal output section CS1 has a fuse F1, a P-channel MOS transistor T
P1, P-channel MOS transistor TN1, and inverters Iv1 to Iv3.

The control signal output section CS2 includes a fuse F2,
P-channel MOS transistor TP2, N-channel M
OS transistor TN2 and inverter Iv4
To Iv6.

The control circuit CT includes P-channel MOS transistors TP3 to TP5, N-channel MOS transistors TN3 to TN5, inverters Iv7 to Iv17, and NAND circuits ND1 and ND2.

The switching circuit (second switching unit) SW1 is a P-channel MOS transistor T
SW1 and an N-channel MOS transistor TSW2, and a switching circuit (first switching unit) S
Similarly, W2 is a P-channel MOS transistor TSW
3 and an N-channel MOS transistor TSW4.

In the control signal output section CS1, one connection of the fuse F1 is supplied with the power supply voltage _VDD which is the operating voltage of the semiconductor integrated circuit device 1, and the other connection is connected to one of the transistors TP1. Are connected.

One connection of the transistor TN1 is connected to the other connection of the transistor TP1, and the transistors TP1 and TN1 constitute an inverter.

The gates of the transistors TP1 and TN1 are connected to receive a reset signal RT input from an external terminal, and the other connection of the transistor TN1 is connected to a reference potential V _SS. I have.

The output of the inverter Iv1 and the input of the inverter Iv2 are connected to the connection between the transistors TP1 and TN1. The input of the inverter Iv1 and the output of the inverter Iv2 are connected to the inverter Iv.
3 are connected, and these inverters Iv
1 and Iv2 constitute a latch circuit.

Further, as shown in FIG. 2, the configuration of the control signal output unit CS2 is the same as that of the control signal output unit CS2.
The power supply voltage _VDD is supplied to one connection of the fuse F2, and one connection of the transistor TP2 is connected to the other connection of the fuse F2.
One connection of the transistor TN2 is connected to the other connection of the transistor TP2.

The gates of the transistors TP2 and TN2 are connected so as to receive a reset signal RT input from an external terminal, and the other connection of the transistor TN2 is connected to a reference potential V _SS. I have.

The connection between the transistors TP2 and TN2 is connected to the output of the inverter Iv4 and the input of the inverter Iv5, respectively. The input of the inverter Iv4 and the output of the inverter Iv5 are connected to the inverter Iv.
6 input units are connected.

As shown in FIG. 3, one output of the transistor TP4 is connected to the output of the inverter Iv3. One connecting portion of the transistor TN4 is connected to the other connecting portion of the transistor PT4.

One output terminal of the transistor TP5 is connected to the output terminal of the inverter Iv6. One connection of the transistor TN5 is connected to the other connection of the transistor PT5.

The power supply voltage _VDD is supplied to one connection of the transistor TP3, and one connection of the transistor TN3 is connected to the other connection. The gates of the transistors TP3 to TP5 and TN3 to TN5 are connected so that a reset signal RT is input.

A reference potential V _SS is connected to the other connection portion of the transistors TN3 to TN5.
P3, TN3, transistors TP4, TN4, and transistors TP5, TN5 each constitute an inverter.

The output of the inverter Iv7 and the inverter Iv are connected to the connection between the transistors TP3 and TN3.
8 are connected to each other, and the transistor T
The output of the inverter Iv9 and the input of the inverter Iv10 are connected to the connection of P4 and TN4, respectively. The output of the inverter Iv11 and the inverter Iv11 are connected to the connection between the transistors TP5 and TN5.
v12 input units are connected to each other.

The inverters Iv7, Iv
8, inverters Iv9, Iv10, and inverter I
Latch circuits are respectively constituted by v11 and Iv12.

The input section of the inverter Iv7, the inverter I
The input of the inverter Iv13 is connected to the output of v8. Inverter Iv9 input, inverter I
The other input of the NAND circuit ND1 is connected to the output of v10, the input of the inverter Iv11,
The output of the inverter Iv12 has a NAND circuit ND
2 are connected to each other.

One input of the NAND circuits ND1 and ND2 is connected to the output of the inverter Iv13. The output of the NAND circuit ND1 is connected to the input of the inverter Iv14, and the output of the NAND circuit ND2 is connected to the inverter Iv16.
Are connected.

The output of the inverter Iv14 is connected to the input of the inverter Iv15 and the switching circuit SW.
2 is connected to the gate of the transistor TSW3. The output terminal of the inverter Iv15 is connected to the gate of the transistor TSW4 forming the switching circuit SW2.

The output of the inverter Iv16 is connected to the input of the inverter Iv17 and the switching circuit SW1.
Is connected to the gate of the transistor TSW2. The output terminal of the inverter Iv17 is connected to the gate of the transistor TSW1 included in the switching circuit SW1.

One connection of transistor TSW1 is connected to one connection of transistor TSW2, and the other connection of transistors TSW1 and TSW2 is connected to one connection of transistors TSW3 and TSW4. ing. The other connection of the transistor TSW3 is connected to the other connection of the transistor TSW4.

One connecting portion of the transistors TSW1 and TSW2 in the switching circuit SW1 becomes a voltage terminal T2, and the other connecting portion of the transistors TSW1 and TSW2 is connected to the transistors TSW3 and TSW4.
A connection portion with one connection portion in (2) becomes the voltage terminal T3. Further, the other connection portion of the transistors TSW3 and TSW4 in the switching circuit SW2 becomes the voltage terminal T1.

As described above, the voltage terminal T1 receives the reference voltage V output from the reference voltage circuit 11 (to 18).
_REF is input, and the common terminal 27 is connected to the voltage terminal T2. The voltage terminal T3 has a reference voltage V such as a boost power supply circuit provided in the DRAM macro 2 (to 9).
A circuit that requires _REF is connected.

Next, the operation of the present embodiment will be described with reference to FIG.
It will be described with reference to the flowchart of FIG.

Here, the reference voltage circuits 11 to 14 laid out above the semiconductor chip and the reference voltage circuits 15 to 18 laid out below are grouped into one group. This will be done for each unit.

First, at the time of the probe test, the reference voltages V in the reference voltage circuits 11 to 14 which are one group and the reference voltage circuits 15 to 18 which are the other group.
_REF is measured (step S101), and a rescue decision is made (step S102).

In the process of step S102, when it is determined that all of the reference voltage circuits 11 to 14, 15 to 18 are acceptable, one of the fuses of the trimming circuits in the reference voltage circuits 11 to 18 is blown. , The reference voltage V _REF is set closer to the design value (step S103). If there is no failure in all the reference voltage circuits 15 to 18, the process ends in step S103.

Further, in the process of step S102,
When a certain reference voltage circuit among the reference voltage circuits 11 to 14 and 15 to 18 is determined to be rejected, trimming is performed only for the reference voltage circuit determined to be passed, and the reference voltage V
_REF is set to be closer to the design value (step S104).

For example, it is assumed that, in the processing in step S102, the reference voltage circuit 11 among the reference voltage circuits 11 to 14, 15 to 18 is determined to be defective. In this case,
Of the one group, only the reference voltage circuits 12 to 14 are trimmed in the process of step S104.

Thereafter, the reference voltage V of the reference voltage circuits 12 to 14 trimmed in the process of step S104
_REF is measured (step S105), and the reference voltage circuits 12 to 14 generate the reference voltage V _REF closest to the design value.
Is detected (step S106).

In the process of step S106, for example, when the reference voltage circuit 12 generates the reference voltage V _REF closest to the design value, it is provided in the reference voltage selection units 19 to 22 of the reference voltage circuits 12 to 14. One of the predetermined fuses F1 and F2 is cut (step S107),
The reference voltage V _REF generated by the reference voltage circuit 12 is
It is supplied as a reference voltage for the boost power supply circuits provided in the M macros 2 to 5.

Next, the operation of the reference voltage selector 19 (-26) will be described with reference to FIGS.

First, the fuses F1, F
2 are connected, and the transistors TP1 to TP
5, a low-level reset signal RT is input to the gates of TN1 to TN5. Here, the reset signal RT
Is a so-called active Hi signal that goes high during the reset period and goes low in other cases.

Therefore, a high-level signal is input to the input portions of the inverters Iv2 and Iv5, and a low-level signal, which is an inverted signal of the high-level signal, is latched and output to the inverters Iv3 and Iv3.
Input to Iv6.

Since a high-level signal is input to one connection portion of the transistors TP4 and TP5, the outputs of the inverters Iv8, Iv10 and Iv12 are latched as low-level signals.

A high-level signal inverted by the inverter Iv13 is input to one input portion of the NAND circuits ND1 and ND2.
1 and ND2, an inverter Iv
10, the low level signal output from Iv12 is input.

The outputs of the NAND circuits ND1 and ND2 go high, and the inverters Iv14 and Iv16
The low-level signal inverted by the transistor TSW2 forming the switching circuit SW1 and the transistor TSW3 forming the switching circuit SW2
Are input to the respective gates.

The signals output from the inverters Iv14 and Iv16 are again inverted by the inverters Iv15 and Iv17 to become high-level signals, and the transistors TSW1 and TSW1 forming the switching circuit SW1 and SW2, respectively.
The switching circuit SW1 is turned off, the switching circuit SW2 is turned on, and the reference voltage V _REF generated by the reference voltage circuit 11 (〜18) via the switching circuit SW2 is input to the gate of the switch SW4. Can be output as a reference voltage.

The common wiring 27 (, 28) and the DRAM
A description will be given of a case where a reference voltage V _REF such as a boost power supply circuit provided in the macros 2 (to 9) is connected.

In this case, the fuses F1 and F2 are cut off, and after the reset operation is completed, the inverter Iv
2 and Iv5, a low-level signal is input, so that an output signal (second control signal) of the inverter Iv3,
And the output signal of inverter Iv6 (first control signal)
Goes low.

Therefore, a low-level signal is input to one connection portion of the transistors TP4 and TP5, and the output of the inverter Iv8 is a low-level signal and the inverter Iv1
The outputs of 0 and Iv12 are latched as high level signals.

A high-level signal inverted by the inverter Iv13 is input to one input of the NAND circuits ND1 and ND2.
1, ND2 also has an inverter Iv
10, the high-level signal output from Iv12 is input.

The outputs of the NAND circuits ND1 and ND2 go low, and the high-level signal inverted by the inverters Iv14 and Iv16 is supplied to the transistor TSW.
2 and the gate of the transistor TSW3.

The low-level signal again inverted by the inverters Iv15 and Iv17 is input to the gates of the transistor TSW1 and the transistor TSW4, so that the switching circuit SW1 is turned on and the switching circuit SW2 is turned off. It is connected to a common wiring 27 (, 28) via a switching circuit SW1.

Further, the reference voltage circuit 11 (〜18), the common wiring 27 (28), and the DRAM macro 2 (〜
The case of connecting the supply destination of the reference voltage V _REF such as the boost power supply circuit of 9) will be described.

In this case, only the fuse F2 is blown, and after the reset operation is completed, a high-level signal is input to the input section of the inverter Iv2,
Since the low level signal is input to the input unit of No. 5, the outputs of the inverters Iv3 and Iv6 become low level and high level, respectively.

A high-level signal and a low-level signal are input to one connection of the transistors TP4 and TP5, and the outputs of the inverters Iv10 and Iv12 are latched as low-level and high-level signals. The output of the inverter Iv8 is a low level signal.

A high-level signal is input to one input of the NAND circuits ND1 and ND2, and a low level signal output from the inverters Iv10 and Iv12 is input to the other input of the NAND circuits ND1 and ND2. Level and high level signals are input.

The output of the NAND circuit ND1 goes high, the output of the NAND circuit ND2 goes low,
The low-level and high-level signals inverted by the inverters Iv14 and Iv16 are output to the transistors TSW2,
And the gate of the transistor TSW3.

The signals inverted again by the inverters Iv15 and Iv17 are input to the gates of the transistor TSW1 and the transistor TSW4, and the switching circuits SW1 and SW2 are turned on, and the reference voltage circuit 11 is turned on via these switching circuits SW1 and SW2.
(~ 18), common wiring 27 (, 28), and DRAM
It is connected to the boost power supply circuit of macro 2 (to 9).

Therefore, as described above, the fuses F1 and F2
, The reference voltage circuit 11 (（18), the common wiring 27 (, 28), and D
The connection destination of the RAM macro 2 (（9) is switched to perform the relief.

Thus, according to the present embodiment, DR
Even if one of the reference voltage circuits provided in the AM macros 2 to 9 becomes defective, it can be remedied by the reference voltage selection units 19 to 26, so that the production yield of the semiconductor integrated circuit device 1 can be improved. .

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, when a defective reference voltage circuit is detected, the reference voltage of the reference voltage circuit that generates the reference voltage closest to the design value is changed to the supply destination circuit of another DRAM macro. , But
The reference voltage generated by another reference voltage circuit may be supplied only to the DRAM macro having the defective reference voltage circuit.

Further, in the above-described embodiment, the reference voltage circuit laid out above the semiconductor chip and the reference voltage circuit laid out below are relieved as separate groups, but there are no restrictions on the wiring layout. For example, both the upper and lower reference voltage circuits may be connected by one common wiring and relieved as one group.

[0083]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the voltage generation circuit switching means provided in each macro cell provides
Even if there is a voltage generation circuit that generates an internal voltage outside the specified range, supply the internal voltage generated by the voltage generation circuit that generates the internal voltage closest to the reference value to the internal circuit provided in each macro cell Therefore, a defective voltage generating circuit can be relieved.

(2) In the present invention, the production yield of the semiconductor integrated circuit device can be improved by the above (1).

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 shows respective DRAs according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a control signal output unit in a reference voltage selection unit provided in an M macro.

FIG. 3 is a circuit diagram of a switching circuit and a control circuit provided in a reference voltage selection unit according to one embodiment of the present invention.

FIG. 4 is a flowchart of a selection switching operation of a reference voltage circuit in a reference voltage selection unit according to one embodiment of the present invention.

[Description of Signs] 1 Semiconductor integrated circuit device 2-9 DRAM macro (macro cell) 10 Logic circuit 11-18 Reference voltage circuit (voltage generation circuit) 19-26 Reference voltage selection unit (voltage generation circuit switching means) 27, 28 Common Wiring T1 to T3 Voltage terminals CS1, CS2 Control signal output unit (selection signal generation unit) SW1 Switching circuit (second switching unit) SW2 Switching circuit (first switching unit) CT control circuit (control signal generation unit) F1 , F2 fuse TP1~TP5 transistor TN1~TN5 transistor Iv1~Iv17 inverter ND1, ND2 NAND circuit TSW1~TSW4 transistor V _REF reference voltage (internal voltage)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Eiji Yamazaki, Inventor 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Masahiro Katayama, Inventor Tokyo 5-22-1, Josuihonmachi, Kodaira-shi F-term (reference) 5F038 AV15 BB07 BG03 DF11 EZ20 in Hitachi Ultra-SII Systems Co., Ltd.

Claims (2)

[Claims] 1. A semiconductor integrated circuit device comprising: two or more macro cells; and a voltage generation circuit for generating a certain level of internal voltage in each of the two or more macro cells, wherein a selection signal is generated. A selection signal generation unit that generates a first control signal based on the selection signal generated by the selection signal generation unit; and a first control signal generated by the control signal generation unit. A first switching unit that supplies the internal voltage generated by the voltage generation circuit to the internal circuit of the macro cell based on the second control signal generated by the control signal generation unit. And a second switching section for controlling connection between the internal voltage input section and the common wiring. 2. A method for switching a certain level of an internal voltage, wherein two or more macro cells are provided, and a voltage generation circuit provided in each of the two or more macro cells generates the voltage. Measuring the internal voltages generated by the device and determining whether or not the internal voltages are within a specified value range. A step of switching the connection destinations of the first and second switching units provided in the circuit switching means and supplying an internal voltage of the voltage generating circuit for generating an internal voltage closest to a reference value to all the internal circuits; A method for switching an internal voltage.