JP5803480B2 - Semiconductor memory device and data reading method - Google Patents

Description

  The present invention relates to a semiconductor memory device and a data reading method.

FIG. 23 shows a main circuit of the read-only semiconductor memory device 110.
The semiconductor memory device 110 includes a memory cell array 111, a column switch 112, a reference level generation circuit 113, and a sense amplifier 114.

  The memory cell array 111 includes a plurality of (only one is shown in FIG. 23) word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC provided at the intersections of the word lines WL and the bit lines BL. Have. Each memory cell MC is a cell transistor T1 having a drain connected to a corresponding bit line BL and a gate connected to a corresponding word line WL.

  The column switch 112 has a plurality of switch circuits CS whose first terminals are respectively connected to the plurality of bit lines BL. Each switch circuit CS has a gate supplied with a column selection signal COL, and a second terminal connected to the sense amplifier 114 via a data bit line DB.

  The reference level generation circuit 113 includes a dummy word line DWL, dummy bit lines DBL0 and DBL1, one dummy cell DMCa provided for two dummy bit lines DBL0 and DBL1, and dummy bit lines DBL0 and DBL1. And an N-channel MOS transistor TN connected to one terminal. The dummy cell DMCa is a dummy transistor DTa having a drain connected to the dummy bit lines DBL0 and DBL1, a source connected to the low potential power supply, and a gate connected to the dummy word line DWL. The transistor TN has a gate connected to the high potential power supply VDD and a second terminal connected to the dummy common line DC.

  In such a semiconductor memory device 110, when data is read from an arbitrary memory cell MC, one word line WL and one bit line BL are activated and connected to the word line WL and the bit line BL. Data written in the memory cell MC is read out to the bit line BL. That is, the potential of the bit line BL changes based on the data written in the memory cell MC. Then, the charges on the bit line BL are transmitted to the sense amplifier 114 through the data bit line DB in response to the column selection signal COL. At this time, in the reference level generation circuit 113, the dummy word line DWL and the dummy bit lines DBL0 and DBL1 are activated, and the dummy transistor DTa is turned on. Then, the potential of the dummy common line DC that is changed by the turned-on dummy transistor DTa is used as the reference level of the sense amplifier 114. In the sense amplifier 114, the potential difference between the data bit line DB and the dummy common line DC is amplified, and the amplified signal is output as read data AX.

  Since the reference level of the sense amplifier 114 is generated by the reference level generation circuit 113 in this way, the differential amplifier type sense amplifier 114 is used even when data of the memory cell MC is read by a single-phase bit line. Thus, data can be read out.

  Patent Document 1 is disclosed as a prior art related to the above-described conventional technology.

Japanese Utility Model Publication No. 55-036479

  However, in the reference level generation circuit 113, in order to generate a desired reference level, the dummy bit lines DBL0 and DBL1 are respectively set so as to reproduce the load (parasitic capacitance) of the bit line BL connected to the memory cell MC. Need to form. Therefore, there is a problem that the layout area is increased by the formation of the dummy bit lines DBL0 and DBL1.

According to one aspect of the present invention, m (m is an integer of 2 or more) word lines, n (n is an integer of 2 or more) bit lines, and intersections between the bit lines and the word lines. Two memory cell arrays having memory cells formed, and at least some dummy cells provided at intersections of the bit lines and dummy word lines, a sense amplifier shared by the two memory cell arrays, and the two memories A control circuit that controls reading of data from the cell array, n column switches each having one terminal connected to the n bit lines, and the other terminal of the n column switches are commonly connected. The common bit line and the two memory cell arrays are a first memory cell array and a second memory cell array, the first memory cell array and the second memory cell array. A plurality of memory blocks each including a re- cell array and the sense amplifier , wherein the sense amplifier is connected to the common bit line of each memory cell array and connected to the first memory cell array in each memory block. The connected common bit lines are connected to each other via a first switch circuit, and the common bit lines connected to the second memory cell array in each memory block are connected via a second switch circuit. When the data is read from one memory cell array, the control circuit is connected to each other, and the column switch corresponding to the memory cell for reading data among the column switches in the one memory cell array and the other memory cell array The n column switches in the memory are turned on, and the one memory cell array Said dummy word lines of the word line and the in the other memory cell array of the inner and activated controlled to produce a reference level of the sense amplifier by the dummy cell, the dummy word lines in the first memory cell array Is activated, the first switch circuit is turned on and the second switch circuit is turned off, while the dummy word line in the second memory cell array is activated. One switch circuit is turned off and the second switch circuit is turned on .

  According to one aspect of the present invention, there is an effect that an increase in layout area can be suppressed.

1 is a block diagram illustrating a semiconductor memory device. FIG. 2 is a block circuit diagram showing an example of the internal configuration of the cell array and column switch of the first embodiment. FIG. 3 is a circuit diagram illustrating an internal configuration example of the sense amplifier according to the first embodiment. FIG. 3 is a block circuit diagram illustrating an example of an internal configuration of a controller according to the first embodiment. 3 is a timing chart showing the operation of the semiconductor memory device according to the first embodiment. Explanatory drawing which shows the dispersion | variation in the electric potential of a data bit line. Explanatory drawing which shows the dispersion | variation in a transistor. The layout diagram of a cell array. The layout diagram of a cell array. 6 is a timing chart showing a method for selecting a dummy word line. (A) is a layout diagram of a cell array, (b) is a timing chart showing a method for selecting a dummy word line. (A) is a layout diagram of a cell array, (b) is a timing chart showing a method for selecting a dummy word line. The block circuit diagram which shows the internal structural example of the cell array and column switch of a modification. The block diagram which shows the semiconductor memory device of 2nd Embodiment. The block circuit diagram which shows the internal structural example of the cell array and column switch of 2nd Embodiment. The block circuit diagram which shows the internal structural example of the controller of 2nd Embodiment. The block diagram which shows the semiconductor memory device of 3rd Embodiment. The block circuit diagram which shows the internal structural example of the controller of 3rd Embodiment. FIG. 10 is a block circuit diagram showing an example of the internal configuration of a cell array and column switch of a fourth embodiment. FIG. 10 is a circuit diagram illustrating an example of an internal configuration of a sense amplifier according to a fourth embodiment. The block circuit diagram which shows the internal structural example of the controller of 4th Embodiment. 10 is a timing chart showing the operation of the semiconductor memory device according to the fourth embodiment. 1 is a block circuit diagram showing a conventional semiconductor memory device.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the semiconductor memory device 1 includes memory cell arrays (cell arrays) 10U and 10D, column switches 20U and 20D, a sense amplifier 30, an output latch 40, a controller 50, and column decoders 70U and 70D. And row decoders 80U and 80D. The semiconductor storage device 1 is a read-only storage device (Read Only Memory: ROM).

  The cell array 10U and the column switch 20U are provided above the sense amplifier 30 in FIG. On the other hand, the cell array 10D and the column switch 20D are provided below the sense amplifier 30 in FIG. These two cell arrays 10U and 10D share the sense amplifier 30.

  The cell array 10U includes m word lines WL0U to WLmU arranged in parallel in the column direction (vertical direction in the drawing) and n (16 in this case) arranged in parallel in the row direction (horizontal direction in the drawing). A plurality of memory cells MC provided at intersections with the bit lines BL0U to BL15U. Each word line WLU (generally indicating word lines WL0U to WLmU) is formed to extend in the row direction, and memory cells MC arranged in the row direction are connected to a common word line WLU. Each bit line BLU (generally showing bit lines BL0U to BL15U) is formed to extend in the column direction, and memory cells MC arranged in the column direction are connected to a common bit line BLU. . These memory cells MC are real cells in which desired data (cell information) is written.

  The cell array 10U has a plurality of dummy cells DMC provided at the intersections between the bit lines BLU and the dummy word lines DWLU formed so as to extend in the row direction. These dummy cells DMC function as a circuit that generates the reference level of the sense amplifier 30 when data is read from the other cell array 10D (when the cell array 10U is not accessed).

  The column switch 20U selects one of the bit lines BL0U to BL15U based on the column selection signals C0U to C15U supplied from the column decoder 70U, and connects the selected bit line BLU to the sense amplifier 30.

  The cell array 10D includes a plurality of word lines WL0D to WLmD arranged in parallel in the column direction and a plurality of 16 (here, 16) bit lines BL0D to BL15D arranged in parallel in the row direction. Memory cells MC. Each word line WLD (generally indicating word lines WL0D to WLmD) is formed to extend in the row direction, and memory cells MC arranged in the row direction are connected to a common word line WLD. Each bit line BLD (generally showing bit lines BL0D to BL15D) is formed to extend in the column direction, and memory cells MC arranged in the column direction are connected to a common bit line BLD. . These memory cells MC are real cells in which desired data is written.

  The cell array 10D has a plurality of dummy cells DMC provided at the intersections of the bit lines BLD and the dummy word lines DWLD formed so as to extend in the row direction. These dummy cells DMC function as a circuit that generates the reference level of the sense amplifier 30 when data is read from the other cell array 10U (when the cell array 10D is not accessed).

  The column switch 20D selects one of the bit lines BL0D to BL15D based on the column selection signals C0D to C15D supplied from the column decoder 70D, and connects the selected bit line BLD to the sense amplifier 30.

  Here, for example, when data is read from the memory cell MC of the cell array 10U, one word line WLU among the plurality of word lines WL0U to WLmU is selected, and one bit of the plurality of bit lines BL0U to BL15U is selected. Line BLU is selected. Then, the data written in the memory cells MC connected to the selected word line WL and bit line BL are read out to the sense amplifier 30. At this time, in the cell array 10D, the dummy word line DWLD is selected, and all the bit lines BL0D to BL15D are selected. Then, the potentials of the bit lines BL0D to BL15D are changed by the dummy cells DMC, and the changed potentials are output to the sense amplifier 30. The voltage generated by the dummy cell DMC becomes the reference level of the sense amplifier 30.

  The sense amplifier 30 is a differential amplifier type sense amplifier. When reading data from the cell array 10U, the sense amplifier 30 amplifies a difference voltage between a minute charge read from the cell array 10U and a reference level generated by the dummy cell DMC of the cell array 10D. On the other hand, when reading data from the cell array 10D, the sense amplifier 30 amplifies a difference voltage between the minute charge read from the cell array 10D and the reference level generated by the dummy cell DMC of the cell array 10U. Then, the sense amplifier 30 outputs the amplified signals AX and AZ to the output latch 40.

The output latch 40 latches the amplified signals AX and AZ output from the sense amplifier 30 and outputs the latched signals as output data A to the outside.
Address signals A0 to Ak, a clock signal CK, and a chip enable signal CE are input to the controller 50 from the outside. The controller 50 includes a predecoder 51, a sense amplifier driver 52, and a dummy word line driver 53. The predecoder 51 predecodes the address signals A0 to Ak and supplies the predecode signal to the row decoders 80U and 80D and the column decoders 70U and 70D. The address signals A0 to Ak are column address signals for selecting column switches, the address signals A4 to Ak-1 are row address signals for selecting word lines, and the address signal Ak. Is an address signal for selecting a cell array.

  The sense amplifier driver 52 generates a sense amplifier enable signal SAE and an equalize signal EQ based on the clock signal CK and the chip enable signal CE and outputs them to the sense amplifier 30.

  The dummy word line driver 53 selects (activates) one of the dummy word lines DWLU and DWLD based on the address signal Ak, the clock signal CK, and the chip enable signal CE. Here, the dummy word line driver 53 changes the potential of the selected dummy word line from the voltage level (L level) of the low potential power supply (ground) to the voltage level (H level) of the high potential power supply VDD (see FIG. 2). Let Specifically, the dummy word line driver 53 activates the dummy word line DWLD of the other cell array 10D when data is read from the one cell array 10U. On the other hand, the dummy word line driver 53 activates the dummy word line DWLU of the cell array 10U when data is read from the cell array 10D.

  The column decoder 70U decodes the predecode signal to generate column selection signals C0U to C15U, and supplies the column selection signals C0U to C15U to the column switch 20U. In the column switch 20U, a predetermined bit line BLU among the bit lines BL0U to BL15U is selected based on the column selection signals C0U to C15U. Specifically, any one of the bit lines BL0U to BL15U is selected when accessing the cell array 10U. When the cell array 10D is accessed (when the cell array 10U is not accessed), all the bit lines BL0U to BL15U are selected.

  The column decoder 70D decodes the predecode signal to generate column selection signals C0D to C15D, and supplies the column selection signals C0D to C15D to the column switch 20D. In the column switch 20D, a predetermined bit line BLD among the bit lines BL0D to BL15D is selected based on the column selection signals C0D to C15D. Specifically, when accessing the cell array 10D, one of the bit lines BL0D to BL15D is selected. When the cell array 10U is accessed (when the cell array 10D is not accessed), all the bit lines BL0D to BL15D are selected.

  Row decoder 80U decodes the predecode signal to select (activate) any one of word lines WL0U to WLmU, that is, raises the potential of a predetermined word line WLU to the H level. Specifically, the row decoder 80U selects one of the word lines WL0U to WLmU when data is read from the cell array 10U (when accessing the cell array 10U). Note that the row decoder 80U does not select all the word lines WL0U to WLmU when data is read from the cell array 10D, that is, when the cell array 10U is not accessed.

  The row decoder 80D decodes the predecode signal and selects any one word line WLD from among the word lines WL0D to WLmD, that is, raises the potential of the predetermined word line WLD to the H level. Specifically, the row decoder 80D selects one of the word lines WL0D to WLmD when accessing the cell array 10D. Note that the row decoder 80D does not select all the word lines WL0D to WLmD when data is read from the cell array 10U, that is, when the cell array 10D is not accessed.

Next, an example of the internal configuration of the cell arrays 10U and 10D and the column switches 20U and 20D will be described with reference to FIG.
The cell array 10U is provided at the intersection of the precharge circuit 11 for precharging each bit line BLU, the memory cell MC provided at the intersection of the word line WLU and the bit line BLU, and the dummy word line DWLU and the bit line BLU. A dummy cell DMC.

  The precharge circuit 11 includes a plurality of switch circuits S1 provided corresponding to the bit lines BL0U to BL15U and connecting the bit lines BL0U to BL15U to the high potential power supply VDD. Each switch circuit S1 is, for example, a P-channel MOS transistor. Each switch circuit S1 has a source connected to the high potential power supply VDD and a drain connected to the corresponding bit line BLU. A precharge signal CH1 is supplied to the gate of each switch circuit S1. These switch circuits S1 are turned on in response to an L-level precharge signal CH1 supplied before the selection of the word line WLU or the bit line BLU. When the switch circuit S1 is turned on, the bit lines BL0U to BL15U are connected to the high potential power supply VDD. That is, the precharge circuit 11 precharges all the bit lines BL0U to BL15U to the voltage level (H level) of the high potential power supply VDD while the precharge signal CH1 is at the L level.

  Each memory cell MC has one cell transistor T1. The cell transistor T1 is, for example, an N channel MOS transistor. The cell transistor T1 storing “0” data has a drain connected to the corresponding bit line BLU, a source connected to the low potential power supply (ground), and a gate connected to the corresponding word line WLU. Therefore, when the word line WLU is selected and the cell transistor T1 is turned on, the bit line BLU becomes the ground level (L level), and data “0” is read. On the other hand, the cell transistor T1 storing “1” data has a drain connected to the corresponding bit line BLU, an open source, and a gate connected to the corresponding word line WLU. Therefore, when the word line WLU is selected and the cell transistor T1 is turned on, the bit line BLU is set to the precharge level (H level), and data “1” is read.

  Each dummy cell DMC has one dummy transistor DT. The dummy transistor DT is, for example, an N channel MOS transistor. The dummy transistor DT has the same electrical characteristics as the cell transistor T1. That is, the dummy transistor DT is a replica transistor of the cell transistor T1. The drain of the dummy transistor DT is connected to the corresponding bit line BLU, the source is connected to the ground, and the gate is connected to the dummy word line DWLU. Of the two bit lines BLU, one bit line BLU has a drain connected to the corresponding bit line BLU, a source opened, and a gate connected to the corresponding dummy word line DWLU. DT1 is provided. The transistor DT1 does not function as a dummy cell DMC (dummy transistor DT). That is, the dummy transistor DT (dummy cell DMC) is provided for n / 2 bit lines BLU among the n bit lines BLU. In other words, among the n transistors connected to the dummy word line DWLU and the n bit lines BLU, the sources of n / 2 dummy transistors DT are connected to the ground, and the remaining n / 2 transistors DT1. The source of is open. Therefore, when the dummy word line DWLU is selected, one dummy transistor DT is provided for two bit lines BLU (for example, bit lines BL0U and BL1U). As a result, the load (parasitic capacitance) of the bit line BLU for one dummy transistor DT is approximately twice the load of the bit line BLU for one cell transistor T1. Therefore, the time constant in the potential change of the bit line BLU when the dummy word line DWLU is selected is about twice the time constant when data is read from the memory cell MC. As a result, when the dummy word line DWLU is selected, the potential of each bit line BLU is the potential when the data “0” is read from the memory cell MC and the potential when the data “1” is read. It becomes an intermediate potential. The intermediate potential generated by the dummy transistor DT is used as a reference level in the sense amplifier 30.

  The column switch 20U has a plurality of column switches SU provided corresponding to the bit lines BL0U to BL15U. The column switch SU is, for example, an N channel MOS transistor. Each column switch SU has a first terminal (for example, drain) connected to the bit line BLU and a second terminal (for example, source) connected to the data bit line DBU. Column selection signals C0U to C15U are supplied to the gates of the column switches SU corresponding to the bit lines BL0U to BL15U, respectively. These column switches SU are turned on in response to H level column selection signals C0U to C15U. When the column switch SU is turned on, the bit line BLU and the data bit line DBU corresponding to the column switch SU are connected. Since all the column selection signals C0U to C15U are at the H level when accessing the cell array 10D, all the column switches SU are turned on, and all the bit lines BL0U to BL15U are commonly connected to the data bit line DBU. .

  The data bit line DBU is connected to the sense amplifier 30. A switch circuit S2 for precharging is connected to the data bit line DBU. The switch circuit S2 is, for example, a P channel MOS transistor. The switch circuit S2 has a drain connected to the data bit line DBU and a source connected to the high potential power supply VDD. A precharge signal CH2 is supplied to the gate of the switch circuit S2. The switch circuit S2 is turned on in response to an L-level precharge signal CH2 supplied before selection of the word line WLU or bit line BLU. When switch circuit S2 is turned on, high potential power supply VDD is connected to data bit line DBU, so that data bit line DBU is precharged to H level.

  The cell array 10D and the column switch 20D have substantially the same configuration as the cell array 10U and the column switch 20U, respectively. For this reason, similar elements are denoted by the same reference numerals or “D” instead of “U” at the end of the reference numerals of the cell array 10U and the column switch 20U, and detailed description of these elements is omitted.

Next, an example of the internal configuration of the sense amplifier 30 will be described with reference to FIG.
The sense amplifier 30 includes P-channel MOS transistors P1 and P2 that connect the data bit lines DBU and DBD and the read bit lines RDBU and RDBD, a precharge circuit 31, a sense amplifier unit 32, and read bit lines RDBU and RDBD, respectively. And inverter circuits 33 and 34 connected to each other.

  A sense amplifier enable signal SAE is supplied to the gates of the transistors P1 and P2. These transistors P1 and P2 are turned on in response to the L level sense amplifier enable signal SAE to connect the data bit lines DBU and DBD to the read bit lines RDBU and RDBD, respectively. The transistors P1 and P2 are separated from the data bit lines DBU and DBD connected to the memory cell MC by disconnecting the read bit lines RDBU and RDBD connected to the sense amplifier unit 32, respectively. This capacitance is made invisible from the sense amplifier 32.

  The precharge circuit 31 is connected to the P-channel MOS transistor P3 connected between the read bit line RDBU and the read bit line RDBD, the P-channel MOS transistor P4 connected to the read bit line RDBU, and the read bit line RDBD. P channel MOS transistor P5. The transistor P4 has a source connected to the high potential power supply VDD and a drain connected to the read bit line RDBU. The source of the transistor P5 is connected to the high potential power supply VDD, and the drain is connected to the read bit line RDBD. An equalize signal EQ is supplied to the gates of the transistors P3, P4 and P5. These transistors P3 to P5 are turned on in response to an L level equalize signal EQ supplied before selection of the word line WLU or bit line BLU. That is, precharge circuit 31 precharges read bit lines RDBU and RDBD to H level while equalize signal EQ is at L level.

  The sense amplifier unit 32 includes a pair of CMOS inverters I1 and I2 whose inputs and outputs are connected to each other, and an N-channel MOS transistor N1 provided between the CMOS inverters I1 and I2 and the ground. The output of the CMOS inverter I1 is connected to the input of the CMOS inverter I2 and the read bit line RDBU. The output of the CMOS inverter I2 is connected to the input of the CMOS inverter I1 and the read bit line RDBD. The CMOS inverters I1 and I2 are connected to the high potential power supply VDD and to the ground through the transistor N1. A sense amplifier enable signal SAE is supplied to the gate of the transistor N1. The transistor N1 is turned on in response to the H level sense amplifier enable signal SAE. That is, the sense amplifier unit 32 is activated in response to the H level sense amplifier enable signal SAE, and the voltage difference between the read bit lines RDBU and RDBD is set to the high potential power supply VDD level (H level) and the ground level (L level). Amplify.

Next, an example of the internal configuration of the controller 50 will be described with reference to FIG.
In the controller 50, the clock signal CK is input to the NAND circuit 54, and the chip enable signal CE is input to the NAND circuit 54 via the inverter circuit 55. The output signal of the NAND circuit 54 is output as a clock signal MCLK via an odd-numbered stage (one stage in FIG. 4) inverter circuit 56. When the clock signal CK transitions to the H level while the chip enable signal CE is at the L level, the clock signal MCLK becomes the H level after the operation delay time of the inverter circuit 56 from the transition. The clock signal MCLK is supplied to the sense amplifier driver 52, the dummy word line driver 53, and the first to third predecoders 51A to 51C.

  In the sense amplifier driver 52, the clock signal MCLK is input to the inverter circuit 57 of the even number stage. The output signal of the inverter circuit 57 is supplied to the NAND circuit 59 via the odd-numbered stage (five stages in FIG. 4) inverter circuit 58 and directly to the NAND circuit 59. An output signal of the NAND circuit 59 is output as the sense amplifier enable signal SAE through an inverter circuit. The operation delay time of the even-numbered inverter circuit 57 corresponds to a waiting time until the sense amplifier 30 is activated after the chip enable signal CE changes to L level and the clock signal MCLK rises to H level. . The operation delay time of the odd-numbered inverter circuit 58 corresponds to the pulse width of the sense amplifier enable signal SAE.

  In the sense amplifier driver 52, the clock signal MCLK delayed by a predetermined time by the even number of inverter circuits is input to the NOR circuit 61, and the sense amplifier enable signal SAE is input to the NOR circuit 61. The output signal of the NOR circuit 61 is output as the equalize signal EQ through the inverter circuit.

  In the controller 50, the clock signal MCLK delayed by a predetermined time by the even number of inverter circuits is input to the NOR circuit 62, and the sense amplifier enable signal SAE is input to the NOR circuit 62. The output signal of the NOR circuit 62 is output as the precharge signals CH1 and CH2 through the inverter circuit.

  The first predecoder 51A receives the clock signal MCLK and the lower 4 bits of column address signals A0 to A3 of the address signals A0 to Ak. The first predecoder 51A operates based on the H level clock signal MCLK, and generates predecode signals PC0 to PC15 based on the column address signals A0 to A3 and their inverted signals. Specifically, in the first predecoder 51A, any one of the predecode signals PC0 to PC15 becomes L level based on the column address signals A0 to A3.

  The second predecoder 51B receives the clock signal MCLK and the row address signals A4 to Ak-1 of the address signals A0 to Ak. The second predecoder 51B operates based on the H level clock signal MCLK, and generates predecode signals PWL0 to PWLm based on the row address signals A4 to Ak-1 and their inverted signals. Specifically, in the second predecoder 51B, any one of the predecode signals PWL0 to PWLm becomes H level based on the row address signals A4 to Ak-1.

  The third predecoder 51C receives the clock signal MCLK, the upper 1-bit address signal Ak of the address signals A0 to Ak, and the inverted signal XAk of the address signal Ak. In the third predecoder 51C, the clock signal MCLK is input to the NAND circuits 63 and 64, and the address signal Ak and the inverted signal XAk are input to the NAND circuits 63 and 64, respectively. An output signal of the NAND circuit 63 is output as a selection signal BLKD through an inverter circuit. The output signal of the NAND circuit 63 is output as the selection signal BLKU via the inverter circuit. In the third predecoder 51C, one of the selection signals BLKU and BLKD becomes H level based on the address signal Ak. Specifically, the selection signal BLKU is at H level when data is read from the cell array 10U, and the selection signal BLKD is at H level when data is read from the cell array 10D.

  In the dummy word line driver 53, the clock signal MCLK delayed by a predetermined time by the even number of inverter circuits is input to the NAND circuits 65 and 66. The selection signal BLKD is input to the NAND circuit 65. The output signal of the NAND circuit 65 is output to the dummy word line DWLU via the inverter circuit. That is, the inversion level of the output signal of the NAND circuit 65 becomes the potential of the dummy word line DWLU. For example, when the cell array 10U is accessed, that is, when the selection signal BLKD is at the L level, the output signal of the NAND circuit 65 becomes the H level regardless of the signal level of the clock signal MCLK, so that the potential of the dummy word line DWLU is L Become a level. On the other hand, when the cell array 10D is accessed, that is, when the selection signal BLKD is at the H level, the output signal of the NAND circuit 65 becomes the L level in response to the rising of the clock signal MCLK, so that the potential of the dummy word line DWLU is Become H level.

  The selection signal BLKU is input to the NAND circuit 66. The output signal of the NAND circuit 66 is output to the dummy word line DWLD through the inverter circuit. That is, the inversion level of the output signal of the NAND circuit 66 becomes the potential of the dummy word line DWLD. For example, when the cell array 10D is accessed, that is, when the selection signal BLKU is at the L level, the output signal of the NAND circuit 66 becomes the H level regardless of the signal level of the clock signal MCLK, so that the potential of the dummy word line DWLD is at the L level. Become a level. On the other hand, when the cell array 10U is accessed, that is, when the selection signal BLKU is at the H level, the output signal of the NAND circuit 66 becomes the L level in response to the rising of the clock signal MCLK, so that the potential of the dummy word line DWLD is Become H level.

Next, an example of the internal configuration of the column decoders 70U and 70D will be described.
The column decoder 70U has 16 NAND circuits 71 to which the predecode signals PC0 to PC15 output from the first predecoder 51A are respectively input. Each NAND circuit 71 receives a selection signal BLKU. The output signal of the NAND circuit 71 is supplied to the corresponding column switch SU (see FIG. 2) as column selection signals C0U to C15U. For example, when the cell array 10U is accessed, that is, when the selection signal BLKU is at the H level, any one of the column selection signals C0U to C15U becomes the H level based on the predecode signals PC0 to PC15. On the other hand, when the cell array 10D is accessed, that is, when the selection signal BLKU is at L level, all the column selection signals C0U to C15U are at H level. As a result, all the column switches SU connected to the bit lines BL0U to BL15U are turned on.

  The column decoder 70D has 16 NAND circuits 72 to which the predecode signals PC0 to PC15 output from the first predecoder 51A are respectively input. Each NAND circuit 72 receives a selection signal BLKD. The output signal of the NAND circuit 72 is supplied to the corresponding column switch SD (see FIG. 2) as column selection signals C0D to C15D.

Next, an internal configuration example of the row decoders 80U and 80D will be described.
The row decoder 80U includes m NAND circuits 81 to which the predecode signals PWL0 to PWLm output from the second predecoder 51B are input, respectively. Each NAND circuit 81 receives a selection signal BLKU. The output signals of the m NAND circuits 81 are output to the corresponding word lines WL0U to WLmU through the inverter circuits, respectively. That is, the inversion level of the output signal of the NAND circuit 81 becomes the potential of the word lines WL0U to WLmU. For example, when the cell array 10U is accessed, that is, when the selection signal BLKU is at H level, the potential of any one of the word lines WL0U to WLmU becomes H level based on the predecode signals PWL0 to PWL15. . On the other hand, when the cell array 10D is accessed, that is, when the selection signal BLKU is at L level, the output signals of all NAND circuits 81 are at H level. For this reason, all the potentials of the word lines WL0U to WLmU become L level.

  The row decoder 80D has m NAND circuits 82 to which predecode signals PWL0 to PWLm output from the second predecoder 51B are input, respectively. Each NAND circuit 82 receives a selection signal BLKD. The output signals of the m NAND circuits 82 are output to the corresponding word lines WL0D to WLmD via the inverter circuits, respectively. That is, the inversion level of the output signal of the NAND circuit 82 becomes the potential of the word lines WL0D to WLmD.

  In this embodiment, the precharge circuit 11 is an example of a first precharge circuit, the switch circuit S2 is an example of a second precharge circuit, the controller 50 is an example of a control circuit, and the data bit lines DBU and DBD are common bit lines. It is an example.

  Next, the operation of the semiconductor memory device 1 will be described with reference to FIG. Note that “#” in the bit lines BL # U and BL # D in FIG. 5 is a bit selected based on the address signals A0 to Ak (specifically, column address signals A0 to A3) shown in FIG. Indicates a line. In FIG. 5, the vertical axis and the horizontal axis are appropriately enlarged and reduced for the sake of brevity.

  First, an operation for reading “0” data from the memory cell MC of the cell array 10D will be described. Specifically, the operation when the address signals A0 to Ak for selecting the memory cells MC connected to the bit line BL0D and the word line WL0D of the cell array 10D are input will be described.

(Precharge operation)
When the chip enable signal CE is at the L level and the clock signal CK rises to the H level (time t1), the clock signal MCLK rises to the H level after a predetermined time has elapsed since the rise. At this time, a precharge operation is performed before starting to read data from the cell array 10D. Specifically, the column decoder 70U outputs H level column selection signals C0U to C15U, and the column decoder 70D outputs H level column selection signals C0D to C15D. As a result, all the column switches SU of the cell array 10U are turned on, and all the bit lines BL0U to BL15U are commonly connected to the data bit line DBU. Further, all the column switches SD of the cell array 10D are turned on, and all the bit lines BL0D to BL15D are commonly connected to the data bit line DBD. Further, the controller 50 outputs L level precharge signals CH1, CH2 and an L level equalize signal EQ, and outputs an L level sense amplifier enable signal SAE. In response to the L level precharge signals CH1 and CH2, the switch circuits S1 and S2 are turned on, and the bit lines BL0U to BL15U, the bit lines BL0D to BL15D, and the data bit lines DBU and DBD are precharged to the H level. Further, the precharge circuit 31 is activated in response to the L level equalize signal EQ, and the read bit lines RDBU and RDBD are precharged to the H level. Since transistors P1 and P2 are turned on in response to the L level sense amplifier enable signal SAE, data bit lines DBU and DBD are connected to read bit lines RDBU and RDBD of sense amplifier 30, respectively. At this time, the sense amplifier 30 is inactivated by the L level sense amplifier enable signal SAE.

(Read operation)
First, when the precharge signals CH1 and CH2 and the equalize signal EQ are shifted from the L level to the H level in response to the H level clock signal MCLK, the precharge operation is terminated and the read operation is started (time t2). ). That is, the switch circuits S1 and S2 are turned off in response to the H level precharge signals CH1 and CH2, and the flow of current from the high potential power supply VDD to the bit lines BLU and BLD and the data bit lines DBU and DBD is cut off. . Further, in response to the H level equalize signal EQ, the precharge circuit 31 is deactivated, and the flow of current from the high potential power supply VDD to the read bit lines RDBU and RDBD is cut off.

  The first to third predecoders 51A to 51C operate based on the H level clock signal MCLK, and predecode signals PC0 to PC15, predecode signals PWL0 to PWLm, and selection signals BLKU and BLKD are generated. Then, the row decoder 80D outputs an H level signal to the word line WL0D and an L level signal to the word lines WL1D to WLmD based on the predecode signals PWL0 to PWLm and the selection signal BLKD. Thereby, in the cell array 10D, the cell transistor T1 connected to the word line WL0D is turned on. The column decoder 70D outputs an H level column selection signal C0D and L level column selection signals C1D to C15D to the column switch SD based on the predecode signals PC0 to PC15 and the selection signal BLKD. As a result, only the column switch SD connected to the bit line BL0D is turned on, so that only the bit line BL0D is connected to the read bit line RDBD of the sense amplifier 30 via the data bit line DBD. At this time, since the bit line BL0D is connected to the ground via the turned-on cell transistor T1, the charge on the bit line BL0D is discharged via the cell transistor T1. As a result, the potential of the bit line BL0D gradually decreases. Further, since the charges on the bit line BL0D are transferred to the data bit line DBD and the read bit line RDBD, the potentials on the data bit line DBD and the read bit line RDBD are gradually lowered in the same manner as the potential on the bit line BL0D.

  On the other hand, the row decoder 80U outputs an L level signal to all of the word lines WL0U to WLmU based on the L level selection signal BLKU. Thereby, in the cell array 10U, all the memory cells MC are turned off. At this time, the dummy word line driver 53 in the controller 50 outputs an H level signal to the dummy word line DWLU based on the L level selection signal BLKU. As a result, all the dummy transistors DT are turned on in the cell array 10U.

  At this time, the column decoder 70U outputs H level column selection signals C0U to C15U to the column switch SU based on the L level selection signal BLKU. Thereby, since all the column switches SU are turned on, all of the bit lines BL0U to BL15U are commonly connected to the read bit line RDBU of the sense amplifier 30 via the data bit line DBU. Then, since the bit lines BL0U to BL15U are connected to the ground via the turned-on dummy transistor DT, the charges on the bit lines BL0U to BL15U are discharged via the dummy transistor DT. As a result, the potentials of the bit lines BL0U to BL15U gradually decrease. Here, in the cell array 10U, one dummy transistor DT is connected to the ground for two bit lines BLU (for example, bit lines BL0U and BL1U). For this reason, the load on the bit line BLU for the dummy transistor DT is approximately twice the load on the bit line BL0D for the cell transistor T1 of the cell array 10D. Therefore, the potential of the read bit line RDBU is gradually decreased from the potential of the read bit line RDBD. Specifically, the potential of the read bit line RDBU is an intermediate potential between the potential when the “0” data is read from the memory cell MC and the potential when the “1” data is read. As a result, a difference is generated between the potential read from the cell transistor T1 and the potential generated by the dummy transistor DT, and a potential difference is generated between the read bit lines RDBU and RDBD.

  Eventually, when the sense amplifier enable signal SAE rises (time t3), the sense amplifier 30 is activated in response to the H level sense amplifier enable signal SAE, and a minute potential difference between the read bit lines RDBU and RDBD is amplified. . As a result, the read bit lines RDBU and RDBD make a complementary transition to the H level and the L level, respectively. Here, the read bit line RDBU transitions to the H level, and the read bit line RDBD transitions to the L level. Then, output data A having the same logic as the logic on the read bit line RDBU (the logic opposite to the logic of the data on the read bit line RDBD), here, the output data A at H level is output from the output latch 40. In this manner, “0” data written in the memory cells MC connected to the bit line BL0D and the word line WL0D can be read.

  Next, an operation for reading “0” data from the memory cell MC of the cell array 10U will be briefly described. Specifically, the operation when the address signals A0 to Ak for selecting the memory cells MC connected to the bit line BL0U and the word line WL0U of the cell array 10U are input will be described.

  Similarly to the above, after the precharge operation, the read operation is started. At this time, in the cell array 10U, the potential of the word line WL0U rises to the H level, and the bit line BL0U is selected in response to the H level column selection signal C0U (time t4). Then, the bit line BL0U is discharged through the cell transistor T1 connected to the word line WL0U and the bit line BL0U, and the potential of the bit line BL0U is lowered. Along with this, the potentials of the data bit line DBU and the read bit line RDBU also decrease.

  On the other hand, in cell array 10D, the potential of dummy word line DWLD rises to H level, and bit lines BL0D to BL15D are selected in response to H level column selection signals C0D to C15D. Then, all the dummy transistors DT of the cell array 10D are turned on, and the potential of the read bit line RDBD becomes the intermediate potential by the dummy transistors DT. As a result, a potential difference is generated between the read bit lines RDBU and RDBD.

  Thereafter, a slight potential difference between the read bit lines RDBU and RDBD is amplified by the sense amplifier 30 activated in response to the H level sense amplifier enable signal SAE. As a result, the read bit line RDBU transitions to the L level, and the read bit line RDBD transitions to the H level. Then, L level output data A having the same logic as the data on the read bit line RDBU is output from the output latch 40. In this way, “0” data written in the memory cells MC connected to the bit line BL0U and the word line WL0U can be read.

  Next, an operation for reading “1” data from the memory cell MC of the cell array 10D will be described. Specifically, the operation when the address signals A0 to Ak for selecting the memory cells MC connected to the bit line BL1D and the word line WL0D of the cell array 10D are input will be described.

  Similarly to the above, after the precharge operation, the read operation is started. At this time, in the cell array 10D, the potential of the word line WL0D rises to the H level, and the bit line BL1D is selected in response to the H level column selection signal C1D. Then, the cell transistor T1 connected to the word line WL0D and the bit line BL1D is selected, but since the source of the cell transistor T1 is in an open state, the potential of the bit line BL1D is H level (precharge level). ).

  On the other hand, in cell array 10U, the potential of dummy word line DWLU rises to H level, and all of bit lines BL0U to BL15U are selected in response to column selection signals C0U to C15U of H level. Then, all the dummy transistors DT of the cell array 10U are turned on, and the potential of the read bit line RDBU becomes the intermediate potential by the dummy transistors DT. As a result, a potential difference is generated between the read bit lines RDBU and RDBD.

  Thereafter, a slight potential difference between the read bit lines RDBU and RDBD is amplified by the sense amplifier 30 activated in response to the H level sense amplifier enable signal SAE. As a result, the read bit line RDBU transitions to the L level, and the read bit line RDBD transitions to the H level. Then, L-level output data A having the same logic as the data on the read bit line RDBU (the logic opposite to the logic on the read bit line RDBD) is output from the output latch 40. In this way, “1” data written in the memory cells MC connected to the bit line BL1D and the word line WL0D can be read.

According to this embodiment described above, the following effects can be obtained.
(1) When reading data from one cell array (for example, cell array 10U), the reference level of the sense amplifier 30 is generated by a dummy cell DMC provided in the other cell array (for example, cell array 10D), that is, a non-accessed cell array. did. Further, the dummy cells DMC are connected to the bit lines BLU and BLD connected to the memory cell MC (real cell). That is, the bit lines BLU and BLD are shared by the memory cell MC and the dummy cell DMC. Thereby, the layout area can be reduced as compared with the case where a bit line different from that of the memory cell MC is formed in the reference level generation circuit (in this case, the dummy cell DMC).

  (2) By the way, the cell transistor T1 and the dummy transistor DT vary in their on-resistance, threshold voltage, transistor size, etc. due to variations in the manufacturing process of the semiconductor integrated circuit and the manufacturing line, for example, and the voltage amplitude varies with the elapsed time of the bit line. Occurs. Due to this, as shown in FIG. 6, the voltage drop of the data bit line DBU of the cell array to be accessed (for example, the cell array 10U) and the voltage drop of the data bit line DBD of the non-accessed cell array (for example, the cell array 10D) Variation occurs. Due to this variation, when the potential of the data bit line DBD becomes lower than the potential of the data bit line DBU when “0” data is read, there arises a problem that data cannot be read normally.

  In contrast, in the present embodiment, when the reference level of the sense amplifier 30 is generated, a plurality (eight in this example) of dummy cells DMC (reference level generation circuit) are operated. As a result, the variation of the dummy transistor DT is averaged, so that the variation of the dummy transistor DT (its on-current Ion) can be made smaller than that of the cell transistor T1, as shown in FIG. Therefore, it is possible to reduce the influence due to the manufacturing variation of the transistor, and to set the reference level of the sense amplifier 30 to a desired level. For this reason, the occurrence of the problem that the potential of the data bit line DBD generated by the dummy cell DMC as described above becomes lower than the potential of the data bit line DBU when “0” data is read can be suitably suppressed.

  Further, at this time, since the bit lines BLU and BLD connected to the memory cell MC are shared by all of the plurality of dummy cells DMC, an increase in layout area can be effectively suppressed.

(Modification of the first embodiment)
In addition, the said 1st Embodiment can also be implemented in the following aspects which changed this suitably.

  The cell arrays 10U and 10D in the first embodiment may be laid out as shown in FIGS. Hereinafter, an arrangement example of a part of m rows × 16 columns of memory cells MC and the dummy cells DMC in the cell arrays 10U and 10D will be described.

First, the layout of the cell array 10U will be described with reference to FIG.
In the region where the memory cell MC (cell transistor T1) is formed, a diffusion region AR arranged in m / 2 rows × 16 columns is formed. Further, in the region where the dummy cell DMC (dummy transistor DT) is formed, a diffusion region DAR arranged in 1 row × 16 columns is formed. Each diffusion region AR, DAR is formed to be elongated in the column direction (vertical direction in the figure). The diffusion regions AR and DAR are defined by, for example, an element isolation insulating film (not shown) of shallow trench isolation (STI).

  In each diffusion region AR, a bit line contact BCT1 is disposed at a substantially central portion. In one diffusion region AR, two cell transistors T1 are formed above and below the bit line contact BCT1, and the bit line contact BCT1 is shared by the two cell transistors T1. In each diffusion region DAR, a bit line contact BCT2 is disposed at a substantially central portion. In one diffusion region DAR, two dummy transistors DT are arranged above and below the bit line contact BCT2, and the bit line contact BCT2 is shared by the two dummy transistors DT.

  Common bit lines BLU (BL0U to BL15U) extending in the column direction are arranged on the plurality of diffusion regions AR and diffusion regions DAR arranged side by side in the column direction. The bit lines BL0U to BL15U are connected to the bit line contacts BCT1 and BCT2 of the diffusion regions AR and DAR.

  On a plurality of diffusion regions AR arranged side by side in the row direction (lateral direction in the figure), two word lines WLU (for example, word lines WL0U,...) Extending in the row direction across each diffusion region AR. WL1U) are arranged above and below the bit line contact BCT1. Specifically, of the two word lines WLU, the even-numbered word line WLU (for example, the word line WL0U) is arranged below the bit line contact BCT1, and the odd-numbered word line WLU (for example, the word line) WL1U) is arranged above the bit line contact BCT1.

  On the plurality of diffusion regions AR arranged side by side in the row direction, plate electrodes CP extending in the row direction across the diffusion regions AR on the upper and lower sides of the word line WLU with respect to the bit line contact BCT1. Are arranged respectively. A low potential side power supply voltage is applied to the plate electrode CP. Here, in the case of the cell transistor T1 in which “0” data is written, a contact for connecting the plate electrode CP and the diffusion region AR is formed in a region A1 where the plate electrode CP and the diffusion region AR overlap. . In the case of the cell transistor T1 in which “1” data is written, no contact is formed in the region A1.

  On the other hand, on a plurality of diffusion regions DAR arranged side by side in the row direction, a pair of dummy word lines DWLU0 and DWLU1 extending in the row direction across the respective diffusion regions DAR are disposed above and below the bit line contact BCT2. Is arranged. Specifically, the dummy word line DWLU0 is disposed below the bit line contact BCT2, and the dummy word line DWLU1 is disposed above the bit line contact BCT2. The pair of dummy word lines DWLU0 and DWLU1 correspond to the dummy word line DWLU in FIG.

  In addition, on the plurality of diffusion regions DAR arranged side by side in the row direction, the bit line contact BCT2 extends in the row direction across the diffusion regions DAR on the upper and lower sides of the dummy word lines DWLU0 and DWLU1. Plate electrodes CP are respectively disposed. A low potential side power supply voltage is applied to the plate electrode CP.

  Here, in the diffusion region DAR connected to the even-numbered bit line BLU (for example, the bit line BL0U) via the bit line contact BCT2, the contact CT is formed above the bit line contact BCT2, and the bit line A contact CT is formed below the contact BCT2. These contacts CT connect the diffusion region DAR and the plate electrode CP. That is, in the diffusion region DAR, two dummy transistors DT are formed above and below the bit line contact BCT2.

  As described above, in the layout of the dummy transistor DT of the present example, the two dummy transistors DT are formed above and below the bit line contact BCT2 in accordance with the shape of the cell transistor T1.

  On the other hand, in the diffusion region DAR connected to the odd-numbered bit line BLU (for example, the bit line BL1U) via the bit line contact BCT2, the contact CT is not formed above and below the bit line contact BCT2. . That is, in this diffusion region DAR, the dummy transistor DT is not formed, but the transistor DT1 (see FIG. 2) whose source is open is formed.

  A region where the dummy transistor DT corresponding to one even-numbered bit line BLU and one odd-numbered bit line BLU is formed is a repeating unit of arrangement. That is, for example, in the region where the dummy transistor DT corresponding to the bit lines BL0U and BL1U is formed and the region where the dummy transistor DT corresponding to the bit lines BL2U and BL3U is formed, the diffusion region DAR, the bit line contact BCT2 and the contact The CT arrangement is the same.

  Next, the layout of the cell array 10D will be described with reference to FIG. The layout of the cell array 10D is different in the vertical relationship in which the cell transistor T1 and the dummy transistor DT are formed, but is basically the same as the layout of the cell array 10U, and thus detailed description thereof is omitted here.

  In the region where the memory cell MC (cell transistor T1) is formed, the even-numbered word line WLD (for example, word line WL0D) is arranged below the bit line contact BCT1, and the odd-numbered word line WLD (for example, word line WLD). The line WL1D) is arranged above the bit line contact BCT1. In the diffusion region AR, two cell transistors T1 are formed around the bit line contact BCT1.

  In the region where the dummy cell DMC (dummy transistor DT) is formed, the dummy word line DWLD0 is disposed below the bit line contact BCT2, and the dummy word line DWLD1 is disposed above the bit line contact BCT2. In the diffusion region DAR, two dummy transistors DT are formed around the bit line contact BCT2.

  The controller 50 (see FIG. 1) when the cell arrays 10U and 10D are laid out in this way, as shown in FIG. 10, for example, when the even-numbered word line WL0D of the cell array 10D is selected, the dummy word of the cell array 10U. Control to select line DWLU0. At this time, the even-numbered word line WL0D is arranged below the bit line contact BCT1, and the plate electrode CP is arranged outside (downside) the word line WL0D. Therefore, when “0” data is written in the selected memory cell MC (cell transistor T1), a current flows from the corresponding bit line BLD toward the plate electrode CP. Therefore, the direction of the current flowing through the cell transistor T1 is downward. On the other hand, dummy word line DWLU0 is also disposed below bit line contact BCT2, and plate electrode CP is disposed below dummy word line DWLU0. For this reason, in the dummy transistor DT, a current flows from the bit line BLU toward the plate electrode CP. Therefore, the direction of the current flowing through the dummy transistor DT is also downward. Thereby, the direction of the current flowing through the selected cell transistor T1 and the direction of the current flowing through the dummy transistor DT can be made the same direction. Therefore, it is possible to suitably suppress a difference in current flowing through each of the transistors T1 and DT due to a difference in shape between the cell transistor T1 and the dummy transistor DT.

  In the above selection method, only the dummy word line DWLU0 is selected, so that one dummy transistor DT is turned on among the two dummy transistors DT formed in the diffusion region DAR. As a result, one dummy transistor DT is operated for two bit lines BLU, so that the load on the bit line BLU for the dummy transistor DT is twice that for the cell transistor T1.

  Similarly, for example, when the odd-numbered word line WL1D of the cell array 10D is selected, the controller 50 selects the dummy word line DWLU1 of the cell array 10U. Thus, when a word line formed below bit line contact BCT1 is selected in one cell array, a dummy word line formed below bit line contact BCT2 is selected in the other cell array. . When a word line formed above the bit line contact BCT1 is selected in one cell array, a dummy word line formed above the bit line contact BCT2 is selected in the other cell array.

  The bit line contact BCT1 is an example of a first contact, the bit line contact BCT2 is an example of a second contact, the diffusion region AR is an example of a first diffusion region, the diffusion region DAR is an example of a second diffusion region, and the plate electrode CP is It is an example of the 1st-4th power supply wiring. The even-numbered word lines WL0U and WL0D are examples of the first word lines, the odd-numbered word lines WL1U and WL1D are examples of the second word lines, and the dummy word lines DWLU0 and DWLD0 are the first dummy word lines. For example, the dummy word lines DWLU1 and DWLD1 are examples of the second dummy word line.

  11B, for example, when an arbitrary word line WLD (for example, word line WL0D or word line WL1D) is selected in one cell array 10D, dummy word line DWLU0 is selected in the other cell array 10U. , DWLU1 may be selected. That is, in the cell array that generates the reference level of the sense amplifier 30, both the two dummy transistors DT formed above and below the bit line contact BCT2 may be turned on. As a result, both the dummy transistor DT whose current direction is upward and the dummy transistor DT whose current direction is downward operate. Therefore, the shape difference between the cell transistor T1 and the dummy transistor DT can be averaged regardless of whether the direction of the current flowing through the cell transistor T1 is downward or upward. Therefore, it is possible to suitably suppress a difference in current flowing through each of the transistors T1 and DT due to the difference in shape.

  In this case, in order to operate one dummy transistor DT for the two bit lines BLU and BLD, as shown in FIG. 11A, for example, two dummy transistors DT are connected to the bit line BL0U. The dummy transistor DT is not formed for the bit lines BL1U to BL3U. The formation region of the dummy transistors DT corresponding to the four bit lines BL0U to BL3U is a repeating unit of arrangement. Although not shown, for the cell array 10D, for example, two dummy transistors DT are formed for the bit line BL0D, and the dummy transistors DT are not formed for the bit lines BL1D to BL3D.

  In addition, as shown in FIG. 12A, the distance between adjacent bit lines may be different. Specifically, the distance between the bit line BL0U and the bit line BL1U, the distance between the bit line BL1U and the bit line BL2U, and the distance between the bit line BL2U and the bit line BL3U are equal. These distances are shorter than the distance between the bit line BL3U and the bit line BL4U. When the distance (pitch) between the bit lines is different, the load (capacitance) of the bit line is changed, so that the current flowing through the cell transistor T1 and the dummy transistor DT is also changed.

  Therefore, as shown in FIG. 12A, for example, a dummy transistor DT having a wide pitch with the left bit line in the drawing and a dummy transistor DT having a narrow pitch with the left bit line in the drawing are operated. The contact CT may be arranged so that Specifically, in the example of FIG. 12A, the bit line contact BCT2 connected to the bit line BL4U is connected to the bit line BL4U having a wide pitch with the bit line BL3U arranged on the left side in the drawing. Contacts CT are formed on the upper and lower sides. In addition, for the bit line BL5U having a narrow pitch with the bit line BL4U arranged on the left side in the drawing, the contact CT is formed up and down across the bit line contact BCT2 connected to the bit line BL5U. Similarly, contacts CT are formed above and below the bit lines BL0U and BL1U with a bit line contact BCT2 connected to the bit lines BL0U and BL1U interposed therebetween.

Although illustration is omitted, the cell array 10D is similarly laid out.
As shown in FIG. 12B, the controller 50 (see FIG. 1) when the cell arrays 10U and 10D are laid out in this way, for example, when the even-numbered word line WL0D of the cell array 10D is selected. The dummy word line DWLU0 is controlled to be selected. As a result, both the dummy transistor DT having a wide pitch with the left bit line in the figure and the dummy transistor DT having a narrow pitch with the left bit line in the figure operate. Therefore, even if the bit line BLD selected in the cell array 10D is a bit line having a wide pitch with the left bit line or a bit line having a narrow pitch with the left bit line, the pitch (shape) of the bit line BLD is selected. The difference in shape between the cell transistor T1 and the dummy transistor DT due to the difference can be averaged. For this reason, it can suppress suitably that a difference arises in the electric current which flows into each transistor T1, DT resulting from these shape differences. Furthermore, since the direction of the current flowing through the selected cell transistor T1 and the direction of the current flowing through the dummy transistor DT can be made the same direction, it is more preferable that a difference occurs in the current flowing through the transistors T1 and DT. Can be suppressed.

  Even in this case, in order to operate one dummy transistor DT for two bit lines BLU and BLD, as shown in FIG. 12A, for example, for bit lines BL0U and BL1U. Two dummy transistors DT are formed, and the dummy transistors DT are not formed for the bit lines BL2U and BL3U. The formation region of the dummy transistors DT corresponding to the four bit lines BL0U to BL3U is a repeating unit of arrangement.

  As shown in FIG. 13, a switch circuit S3 for short-circuiting between the bit lines BL0U to BL15U may be provided for the cell array 10U. Further, a switch circuit S4 for short-circuiting between the bit lines BL0D to BL15D may be provided for the cell array 10D.

  The switch circuit S3 is provided in the vicinity (directly above or directly below) of the dummy cell DMC. The switch circuit S3 is, for example, a P channel MOS transistor. In the switch circuit S3, the first terminal and the second terminal are respectively connected to the adjacent bit lines BLU, and the control signal XDWLU is supplied to the control terminal. Each switch circuit S3 is turned on in response to an L level control signal XDWLU. When the switch circuit S3 is turned on, all the bit lines BL0U to BL15U are short-circuited. Here, the control signal XDWLU is a signal obtained by logically inverting the signal output to the dummy word line DWLU. Therefore, when the dummy word line DWLU is activated and the reference level of the sense amplifier 30 is generated by the dummy cell DMC, the switch circuit S3 is turned on in response to the L level control signal XDWLU, and the bit lines BL0U to BL15U are turned on. Everything is shorted.

  By the way, for example, when all the bit lines BL0U to BL15U are selected only by the column switch SU, the load (parasitic capacitance) of the bit line BLU becomes difficult to see from the dummy cell DMC due to the resistance of the column switch SU. For example, the dummy cell DMC connected to the bit line BL0U is connected to the bit line BL1U via the two column switches SU, and the load on the bit line BL1U becomes difficult to see. Then, since the bit line load seen from the dummy cell DMC is smaller than the actual bit line load (a bit line load twice that of the memory cell MC), the reference level of the sense amplifier 30 generated by the dummy cell DMC is “0” data. It approaches the potential at the time of reading. On the other hand, in the above configuration, the switch circuit S3 that short-circuits all the bit lines BL0U to BL15U when the dummy word line DWLU is activated is provided. Thereby, since the parasitic capacitance of the bit line BLU can be surely seen from the dummy cell DMC, a desired reference level can be suitably generated by the dummy cell DMC.

  The switch circuit S4 is provided in the vicinity (directly above or directly below) of the dummy cell DMC. The switch circuit S4 is, for example, a P channel MOS transistor. In the switch circuit S4, the first terminal and the second terminal are respectively connected to the adjacent bit lines BLD, and a control signal XDWLD is supplied to the control terminal. Here, the control signal XDWLD is a signal obtained by logically inverting the signal output to the dummy word line DWLD. Therefore, when the dummy word line DWLD is activated and the reference level of the sense amplifier 30 is generated by the dummy cell DMC, the switch circuit S4 is turned on in response to the L level control signal XDWLD, and the bit lines BL0D to BL15D Everything is shorted.

The switch circuits S3 and S4 are an example of a third switch circuit.
The precharge circuit 11 in the cell arrays 10U and 10D of the first embodiment may be omitted. In this case, for example, before reading data from the cell arrays 10U and 10D, the bit lines BLU and BLD and the data bit lines DBU and DBD may be precharged to H level using the switch circuit S2.

(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description of these elements is omitted. Hereinafter, the difference from the first embodiment will be mainly described.

  In the first embodiment, two cell arrays 10U and 10D arranged in parallel in the column direction share one sense amplifier 30, and when reading data from one cell array, the dummy cells DMC provided in the other cell array The reference level of the sense amplifier 30 is generated. On the other hand, in the semiconductor memory device 2 of the present embodiment, as shown in FIG. 14, two cell arrays 12U and 12D arranged in parallel in the row direction share one sense amplifier 30 and receive data from one cell array. When reading, the reference level of the sense amplifier 30 is generated by the dummy cell provided in the other cell array. In such two cell arrays 12U and 12D, the word lines WL0 to WLm are shared and the dummy word line DWL is shared.

  Next, an example of the internal configuration of the cell arrays 12U and 12D will be described with reference to FIG. Here, for simplification of the drawing, only one word line WL is illustrated as a word line WL (word lines WL0 to WLm are generally shown).

  In the cell array 12U, an AND circuit 13U is provided for each word line WL. A corresponding word line WL is connected to the AND circuit 13U and a selection signal BSU is input. An internal word line SWLU formed inside the cell array 12U is connected to the output terminal of the AND circuit 13U. Here, the selection signal BSU is a signal obtained by delaying the selection signal BLKU by the operation delay time of the even-numbered inverter circuit 66U in the controller 50A shown in FIG. Therefore, the selection signal BSU is a signal that becomes H level when the cell array 12U is accessed and becomes L level when the cell array 12U is not accessed. In the row decoder 80, the address signals A4 to Ak-1 are decoded, and any one of the word lines WL0 to WLm is activated. Therefore, in FIG. 15, when the word line WL is activated when the cell array 12U is accessed, the output signal of the AND circuit 13U becomes H level, and the potential of the internal word line SWLU becomes H level. In other words, the AND circuit 13U performs the same function as the NAND circuit 81 of the row decoder 80U shown in FIG.

  The cell array 12U is provided with an AND circuit 14U connected to the dummy word line DWL. The selection signal BSU is input to the AND circuit 14U via an inverter circuit. A dummy word line DWLU formed inside the cell array 12U is connected to the output terminal of the AND circuit 14U. Here, in the dummy word line driver 53A shown in FIG. 16, a signal obtained by delaying the clock signal MCLK by the even number of inverter circuits 67 by a predetermined time is output to the dummy word line DWL. Therefore, in FIG. 15, when the cell array 12U is not accessed, when a predetermined time elapses from the rising edge of the clock signal MCLK, the output signal of the AND circuit 14U becomes H level, and the potential of the dummy word line DWLU becomes H level. In other words, the AND circuit 14U performs the same function as the NAND circuit 65 of the dummy word line driver 53 shown in FIG.

  The cell array 12U includes a memory cell MC (cell transistor T1) provided at the intersection of the internal word line SWLU and the bit line BLU, and a dummy cell DMC (dummy) provided at the intersection of the dummy word line DWLU and the bit line BLU. Transistor DT). Each of the bit lines BL0U to BL15U is connected to a common data bit line DBU via a column switch SU to which column selection signals C0U to C15U are input, and further connected to a sense amplifier 30 via a data bit line DBU. Yes.

  Since the cell array 12D has substantially the same configuration as that of the cell array 12U, similar elements are denoted by the same reference numerals or “D” instead of “U” at the end of the reference numerals of the cell array 12U. A detailed description of the elements is omitted. As shown in FIG. 16, the selection signal BSD supplied to the cell array 12D is generated by delaying the selection signal BLKD by the operation delay time of the even-numbered inverter circuit 66D. Therefore, the selection signal BSD is a signal that becomes H level when the cell array 12D is accessed and becomes L level when the cell array 12D is not accessed.

  In such a semiconductor memory device 2, as in the first embodiment, for example, when data is read from one cell array 12U, the dummy word line DWLD of the other cell array 12D is activated and the column selection signal C0D is activated. All of .about.C15D become H level and all of the bit lines BL0D to BL15D are selected. As a result, the reference level of the sense amplifier 30 is generated by the dummy cell DMC (dummy transistor DT) in the conductive state.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIGS. 17 and 18. The same members as those shown in FIGS. 1 to 16 are denoted by the same reference numerals, and detailed description of these elements is omitted. Hereinafter, the difference from the second embodiment will be mainly described.

  As shown in FIG. 17, the semiconductor memory device 3 has a plurality (three in FIG. 17) of memory blocks MB0 to MB2. One memory block corresponds to one data (I / O) terminal (not shown). That is, data read from each of the memory blocks MB0 to MB2 is output from one corresponding I / O terminal.

  Each of the memory blocks MB0 to MB2 includes cell arrays 12U and 12D and column switches 20U and 20D, and a sense amplifier 30 shared by the two cell arrays 12U and 12D. In memory block MB0, column switches 20U and 20D are connected to sense amplifier 30 via data bit lines DBU0 and DBD0, respectively. In memory block MB1, column switches 20U and 20D are connected to sense amplifier 30 via data bit lines DBU1 and DBD1, respectively. In memory block MB2, column switches 20U and 20D are connected to sense amplifier 30 via data bit lines DBU2 and DBD2, respectively.

  Data bit lines DBD0 to DBD2 are connected to each other via a transfer gate G0. These transfer gates G0 are turned on in response to an H level control signal φ0 and turned off in response to an L level control signal φ0. The data bit lines DBU0 to DBU2 are connected to each other via a transfer gate G1. The transfer gate G1 is turned on in response to an H level control signal φ1 and turned off in response to an L level control signal φ0.

  Here, the control signals φ0 and φ1 are complementary signals. For example, when the cell array 12U is accessed, the control signals φ0 and φ1 become the H level and the L level, respectively. For this reason, when the cell array 12U is accessed, the transfer gate G0 is turned on in response to the H level control signal φ0, and the transfer gate G1 is turned off in response to the L level control signal φ1. Thereby, data bit lines DB0U to DB2U are disconnected from other data bit lines, and a plurality of data bit lines DBD0 to DBD2 are connected to each other. In this manner, the reference level of the sense amplifier 30 is generated by the dummy cells DMC (see FIG. 15) provided in the plurality of cell arrays 12D connected to the plurality of data bit lines DBD0 to DBD2.

Next, the control signals φ0 and φ1 will be described in detail.
As shown in FIG. 18, in the controller 50B, the clock signal MCLK delayed by a predetermined time by the even number of inverter circuits is input to the NAND circuit 68, and the selection signal BLKU is input to the NAND circuit 68. Further, the NAND circuit 68 receives the output signal SAE1 of the NAND circuit 59 of the sense amplifier driver 52. An output signal of the NAND circuit 68 is output as the control signal φ0 through an inverter circuit. This control signal φ0 is at the H level only when the cell array 12U is accessed, that is, when the selection signal BLKU is at the H level, while the clock signal MCLK is at the H level and the output signal SAE1 of the NAND circuit 59 is at the H level. In response to the H level control signal φ0, transfer gate G0 is turned on, and data bit lines DBD0 to DBD2 are connected to each other. Control signal φ0 falls to L level in response to the fall of output signal SAE1 of NAND circuit 59 when cell array 12U is accessed. Therefore, before the sense amplifier 30 is activated in response to the H level sense amplifier enable signal SAE, the control signal φ0 falls to the L level. Thus, before activation of sense amplifier 30, data bit lines DBD0 to DBD2 are disconnected from other data bit lines.

  On the other hand, control signal φ0 is at L level in response to L level selection signal BLKU when cell array 12D is accessed, that is, when selection signal BLKU is at L level. In response to control signal φ0 at L level, transfer gate G0 is turned off, and data bit lines DBD0 to DBD2 are disconnected from other data bit lines.

  Similarly, in the controller 50B, the clock signal MCLK delayed by a predetermined time by the even number of inverter circuits is input to the NAND circuit 69, and the selection signal BLKD and the output signal SAE1 of the NAND circuit 59 are input to the NAND circuit 69. The output signal of the NAND circuit 69 is output as the control signal φ1 through the inverter circuit.

  The cell array 12D is an example of the first memory cell array, the cell array 12U is an example of the second memory cell array, the transfer gate G0 is an example of the first switch circuit, the transfer gate G1 is an example of the second switch circuit, and the data bit line DBU0. ˜DBU2 is an example of a common bit line, and the data bit lines DBD0 to DBD2 are an example of a common bit line.

According to the embodiment described above, the following effects can be obtained in addition to the effects (1) and (2) of the first embodiment.
(3) When generating the reference level of the sense amplifier 30, the dummy cells DMC provided in the plurality of cell arrays 12U and 12D are operated. As a result, the number of dummy cells DMC used when generating the reference level can be increased, so that it is possible to reduce the influence of variations in the characteristics of the dummy cells DMC (dummy transistors T1) due to manufacturing variations.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 18 are denoted by the same reference numerals, and detailed description of these elements is omitted. Hereinafter, the difference from the first embodiment will be mainly described.

  In the first embodiment, the two cell arrays 10U and 10D share one sense amplifier 30, and when reading data from one cell array, the reference level of the sense amplifier 30 is set by the dummy cell DMC provided in the other cell array. Generated. In contrast, in the semiconductor memory device 4 of the present embodiment, the two cell arrays 15U and 15D share one sense amplifier 90, and when reading data from one cell array, the dummy cell DMC provided in the other cell array is used. A latch signal La that determines the latch timing of the sense amplifier 90 is generated.

  As shown in FIG. 19, the cell array 15U includes a memory cell MC provided at the intersection of the word line WLU and the bit line BLU, a dummy cell DMC provided at the intersection of the dummy word line DWLU and the bit line BLU, And a precharge circuit 11 for precharging the bit line BLU to the voltage level of the high potential power supply VDD.

  Each memory cell MC has one cell transistor T1. Each dummy cell DMC has one dummy transistor DT. The dummy transistor DT has the same electrical characteristics as the cell transistor T1. That is, the dummy transistor DT is a replica transistor of the cell transistor T1. Each dummy transistor DT has a drain connected to the corresponding bit line BLU, a source connected to the ground, and a gate connected to the dummy word line DWLU. This dummy transistor DT is provided for all the bit lines BL0U to BL15U.

  A column switch SU is connected to each of the bit lines BL0U to BL15U. Each column switch SU has a first terminal (for example, drain) connected to the bit line BLU and a second terminal (for example, source) connected to the data bit line DBU and the NAND circuit 16U. Here, when the cell array 15U is not accessed, all the column selection signals C0U to C15U become H level and all the column switches SU are turned on. Therefore, when the cell array 15U is not accessed, all the bit lines BL0U to BL15U are commonly connected to the NAND circuit 16U. The control signal BLKUX is input to the NAND circuit 16U. A control signal U1 is output from the NAND circuit 16U. Here, the control signal BLKUX is a signal generated by delaying the selection signal BLKD by the operation delay time of the even number of inverter circuits 101 in the controller 50C shown in FIG. For this reason, the control signal BLKUX becomes H level when the cell array 15D is accessed, and becomes L level when the cell array 15D is not accessed. Therefore, when the cell array 15D is not accessed, the H level control signal U1 is output regardless of the data bit line DBU, and when the cell array 15D is accessed, the inverted signal of the data bit line DBU is output as the control signal U1.

  The data bit line DBU is connected to the main bit line MBL0 via the transfer gate G2. The transfer gate G2 is turned on in response to the L level control signal BLKUX and turned off in response to the H level control signal BLKUX. Therefore, when the cell array 15D is not accessed, the transfer gate G2 is turned on, and the data bit line DBU is connected to the sense amplifier 90 via the main bit line MBL0. On the other hand, when the cell array 15D is accessed, the transfer gate G2 is turned off, the data bit line DBU is disconnected from the main bit line MBL0, and the data bit line DBU is disconnected from the sense amplifier 90.

  Since the cell array 15D has substantially the same configuration as the cell array 15U, similar elements are denoted by the same reference numerals or “D” instead of “U” at the end of the reference numerals of the cell array 15U. A detailed description of the elements is omitted.

  The column switch SD connected to each of the bit lines BL0D to BL15D has a first terminal (for example, drain) connected to the bit line BLD and a second terminal (for example, source) connected to the data bit line DBD and the NAND circuit 16D. It is connected. Here, when the cell array 15D is not accessed, all the column selection signals C0D to C15D become H level and all the column switches SD are turned on. Therefore, when the cell array 15D is not accessed, all the bit lines BL0D to BL15D are commonly connected to the NAND circuit 16D. The control signal BLKDX is input to the NAND circuit 16D. A control signal D1 is output from the NAND circuit 16D. Here, the control signal BLKDX is a signal generated by delaying the selection signal BLKU by the operation delay time of the even-numbered inverter circuit 102 in the controller 50C shown in FIG. Therefore, the control signal BLKDX becomes H level when the cell array 15U is accessed, and becomes L level when the cell array 15U is not accessed. Therefore, when the cell array 15U is not accessed, the H level control signal D1 is output regardless of the data bit line DBD, and when the cell array 15U is accessed, the inverted signal of the data bit line DBU is output as the control signal U1.

  The data bit line DBD is connected to the data bit line MBL0 via the transfer gate G3. The transfer gate G3 is turned on in response to the L level control signal BLKDX and turned off in response to the H level control signal BLKDX.

Next, an example of the internal configuration of the sense amplifier 90 will be described with reference to FIG.
In the sense amplifier 90, the potential of the main bit line MBL0 is supplied to the latch circuit 91. The latch circuit 91 includes an inverter circuit 91a in which the main bit line MBL0 is connected to the input terminal, an inverter circuit 91b in which the output terminal of the inverter circuit 91a is connected to the input terminal, and the output terminal is connected to the input terminal of the inverter circuit 91a. And have. Although not shown, the high potential power supply VDD and the ground are connected to the inverter circuits 91a and 91b. The latch circuit 91 determines the potential of the main bit line MBL0 and outputs it to the transfer gate 92 as H level or L level read data AX.

  One end of the transfer gate 92 is connected to the output terminal of the latch circuit 91 (inverter circuit 91 a), and the other end is connected to the input terminal of the latch circuit 93. Transfer gate 92 is formed by connecting a P-channel MOS transistor and an N-channel MOS transistor in parallel. The transfer gate 92 is turned on in response to the L level latch signal La and turned off in response to the H level latch signal La.

  The latch circuit 93 includes inverter circuits 94 a and 94 b and a transfer gate 95. A transfer gate 95 is interposed between the input terminal of the inverter circuit 94a and the output terminal of the inverter circuit 94b.

  Transfer gate 95 is formed by connecting a P-channel MOS transistor and an N-channel MOS transistor in parallel. The transfer gate 95 is turned on in response to the latch signal La at the H level and turned off in response to the latch signal La at the L level. Therefore, the transfer gate 95 is turned off when the transfer gate 92 is turned on, and the transfer gate 95 is turned on when the transfer gate 92 is turned off.

The signal latched by the latch circuit 93 is output to the outside as output data A through the inverter circuit 96.
Next, the latch signal La supplied to the transfer gates 92 and 95 of the sense amplifier 90 will be described. The latch signal La is generated based on the control signals U1 and D1 in the controller 50C shown in FIG.

  Specifically, the control signal U1 generated in the cell array 15U is supplied to the NAND circuit 104 via the odd-numbered inverter circuit 103 (five stages in FIG. 21) and also directly supplied to the NAND circuit 104. Further, the signal D1 generated by the cell array 15D is supplied to the NAND circuit 106 via the odd-numbered stage (five stages in FIG. 21) inverter circuit 105 and directly to the NAND circuit 106. Output signals from the NAND circuits 104 and 106 are input to the NAND circuit 107. The output signal of the NAND circuit 107 is supplied to the NAND circuit 109 via an odd-numbered stage (five stages in FIG. 21) inverter circuit 108 and directly to the NAND circuit 109. The output signal of the NAND circuit 109 is output as the latch signal La.

Next, the operation of the semiconductor memory device 4 will be described with reference to FIG. In FIG. 22, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
Here, an operation in the case of reading “0” data from the memory cell MC of the cell array 15D will be described. Specifically, the operation when the address signals A0 to Ak for selecting the memory cells MC connected to the bit line BL0D and the word line WL0D of the cell array 15D are input will be described.

(Precharge operation)
First, a precharge operation is performed before reading data from the cell array 15D. More specifically, when the chip enable signal CE is at the L level and the clock signal CK rises to the H level, the clock signal MCLK rises to the H level after a predetermined time has elapsed from the rise (time t6). Based on the H level clock signal MCLK and the address signals A0 to Ak, the H level column selection signal C0D and the L level column selection signals C1D to C15D are output to the column switch SD (time t7). As a result, only the column switch SD connected to the bit line BL0D is turned on. At this time, since the transfer gate G3 is turned on in response to the L level control signal BLKDX, the bit line BL0D is connected to the sense amplifier 90 via the data bit line DBD and the main bit line MBL0. Further, H level column selection signals C0U to C15U are output based on the H level clock signal MCLK and the address signals A0 to Ak, and all the column switches SU are turned on. At this time, since the transfer gate G2 is turned off in response to the control signal BLKUX at the H level, the bit lines BL0U to BL15U are commonly connected to the NAND circuit 16U.

  Further, only the word line WL0D among the word lines WL0D to WLmD is activated based on the H level clock signal MCLK and the address signals A0 to Ak. Thereby, in the cell array 15D, the cell transistor T1 connected to the word line WL0D is turned on. Also, the dummy word line DWLU is activated based on the H level clock signal MCLK and the address signals A0 to Ak. Thereby, in the cell array 15U, the dummy transistor DT is turned on.

  Further, based on the H level clock signal MCLK, the L level precharge signals CH1 and CH2 are output for a predetermined period. Then, the switch circuits S1 and S2 are turned on in response to the L level precharge signals CH1 and CH2, and the bit lines BL0U to BL15U, the bit line BL0D, the data bit lines DBU and DBD, and the main bit line MBL0 are precharged to the H level. Charged. Thereafter, when the predetermined period elapses (time t8), the precharge signals CH1 and CH2 transition to the H level, and the switch circuits S1 and S2 are turned off in response to the H level precharge signals CH1 and CH2. The precharge operation ends. In this precharge period, the signal U1 output from the NAND circuit 16U of the cell array 15U falls to the L level. On the other hand, the signal D1 output from the NAND circuit 16D of the cell array 15D is held at the H level because the control signal BLKDX is at the L level. At this time, the output signal of the NAND circuit 104 becomes H level, and the output signal of the NAND circuit 106 becomes H level. Therefore, the output signal of the NAND circuit 107 becomes L level, and the latch signal La becomes H level.

(Read operation)
When the precharge operation ends (time t8), the charge on the bit line BL0D is discharged through the cell transistor T1 that is turned on. As a result, the potential of the bit line BL0D gradually decreases. Further, since the charges of the bit line BL0D are transferred to the data bit line DBD and the main bit line MBL0, the potentials of the data bit line DBD and the main bit line MBL0 gradually decrease in the same manner as the bit line BL0D. At this time, in the sense amplifier 90, since the transfer gate 92 is turned off in response to the latch signal La at the H level, the potential of the main bit line MBL0 is latched by the latch circuit 91 and read out output from the latch circuit 91. Data AX does not reach the latch circuit 93 through the transfer gate 92. At this time, since the transfer gate 95 is turned on in response to the H level latch signal La, the read data AX is not yet latched by the latch circuit 93, and the previous data is held.

  On the other hand, in the cell array 15U, after the precharge operation, the charges of the bit lines BL0U to BL15U are discharged through the turned on dummy transistor DT. As a result, the potentials of the bit lines BL0U to BL15U gradually decrease.

  Eventually, when the potential of the bit lines BL0U to BL15U decreases and the control signal U1 output from the NAND circuit 16U transitions to the H level, the output signal of the NAND circuit 104 becomes the L level. Then, since the output signal of the NAND circuit 107 becomes H level, the latch signal La becomes L level for the operation delay time of the inverter circuits 103 and 108. In response to the L level latch signal La, the transfer gate 92 of the sense amplifier 90 is turned on and the transfer gate 95 is turned off. As a result, the read data AX input to the latch circuit 91 immediately before the transfer gate 92 is turned on is output as output data A through the transfer gate 92. At this time, in this example, since the potential of the main bit line MBL0 falls to approximately L level and the H level read data AX is output from the latch circuit 91, the H level read data AX is output as the output data A. Is done. Thus, the read data AX can be normally output by setting the output timing of the transfer gate 92 using the dummy transistor DT. Specifically, the dummy transistor DT is a replica transistor of the cell transistor T1, and a load similar to that of the cell transistor T1 is connected thereto. For this reason, the potentials of the bit lines BLU and BLD that are discharged by the dummy transistor DT and the cell transistor T1 drop in substantially the same manner. Then, after the bit line discharged by the dummy transistor DT approaches the L level and the control signal U1 output from the NAND circuit 16U transitions to the H level, the L level latch signal La instructing the output at the transfer gate 92 is generated. Generated. In other words, after the main bit line MBL0 discharged by the cell transistor T1 approaches the L level and the output signal of the inverter circuit 91a in the latch circuit 91, that is, the read data AX transitions to the H level, the L level latch signal La Is generated. Therefore, data read from the cell array can be output normally.

According to this embodiment described above, the following effects can be obtained.
(1) When reading data from one cell array (for example, the cell array 15U), the latch signal La supplied to the sense amplifier 90 by the dummy cell DMC provided in the other cell array (for example, the cell array 15D), that is, the non-accessed cell array, Generated. Further, the dummy cells DMC are connected to the bit lines BLU and BLD connected to the memory cell MC (real cell). That is, the bit lines BLU and BLD are shared by the memory cell MC and the dummy cell DMC. As a result, the layout area can be reduced as compared with the case where a bit line different from that of the memory cell MC is formed in the latch timing generation circuit (here, the dummy cell DMC).

  (2) By the way, the cell transistor T1 and the dummy transistor DT vary in their on-resistance, threshold voltage, transistor size, etc. due to variations in the manufacturing process of the semiconductor integrated circuit and the manufacturing line, for example, and the voltage amplitude varies with the elapsed time of the bit line. Occurs. As a result, a variation occurs in the voltage drop of the bit line BLD of the cell array to be accessed (for example, the cell array 15D) and the voltage drop of the bit line BLU in the non-accessed cell array (for example, the cell array 15U). Due to this variation, when the potential of the data bit line DBU reaches the L level extremely earlier than the potential of the data bit line DBU when “0” data is read, there is a problem that data cannot be read normally.

  On the other hand, in the present embodiment, when the latch signal La is generated, a plurality (16 in this example) of dummy cells DMC (latch timing generation circuit) are operated. Thereby, since the variation of the dummy transistor DT is averaged, the variation of the characteristic of the dummy transistor DT can be reduced. Therefore, it is possible to reduce the influence due to the manufacturing variation of the transistors, and to generate the L level latch signal La at a desired timing.

  Further, at this time, since the bit lines BLU and BLD connected to the memory cell MC are shared by all of the plurality of dummy cells DMC, an increase in layout area can be effectively suppressed.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In the second and third embodiments, a precharge circuit 11 that precharges the bit lines BLU and BLD to the H level may be provided as in the first embodiment.

In each of the above embodiments, a plurality of dummy cells DMC are provided. For example, only one dummy cell DMC may be provided.
In the first to third embodiments, dummy cells DMC are provided for n / 2 bit lines BLU, BLD out of n bit lines BLU, BLD. For example, the dummy cells DMC may be provided in all of the n bit lines BLU and BLD. In this case, for example, the dummy transistor DT is formed so that the on-resistance of the dummy transistor DT of the dummy cell DMC is twice the on-resistance of the cell transistor T1 of the memory cell MC.

The various embodiments described above can be summarized as follows.
(Appendix 1)
Two memory cell arrays, a sense amplifier shared by the two memory cell arrays, and a control circuit for controlling data reading from the two memory cell arrays,
Each of the memory cell arrays is
m word lines (m is an integer greater than or equal to 2), n (n is an integer greater than or equal to 2) bit lines, memory cells provided at the intersections of the bit lines and the word lines, and at least a part A dummy cell provided at an intersection of the bit line and the dummy word line,
The control circuit controls to activate the dummy word line of the other memory cell array and generate a reference level of the sense amplifier by the dummy cell when reading data from one memory cell array. Semiconductor memory device.
(Appendix 2)
The memory cell is a cell transistor having a gate connected to the word line and a drain connected to the bit line,
The dummy cell is a replica transistor of the cell transistor having a gate connected to the dummy word line, a drain connected to the bit line, and a source grounded,
2. The semiconductor memory device according to appendix 1, wherein the dummy cell is provided at an intersection of (n / 2) bit lines of the n bit lines and the dummy word line.
(Appendix 3)
N column switches each having one terminal connected to the n bit lines;
A common bit line to which the other terminals of the n column switches are connected in common,
The sense amplifier is connected to the common bit line of each memory cell array,
When reading data from one memory cell array, the control circuit includes a column switch corresponding to a memory cell from which data is read out of the column switches in the one memory cell array and the n switches in the other memory cell array. 3. The semiconductor memory device according to claim 1, wherein the column switch is turned on to activate the word line in the one memory cell array and the dummy word line in the other memory cell array.
(Appendix 4)
A first precharge circuit for precharging each bit line to a predetermined potential;
A second precharge circuit for precharging the common bit line to the predetermined potential;
The control circuit activates the first precharge circuit and the second precharge circuit by turning on the n column switches in each memory cell array when reading data from one memory cell array. After the n bit lines of each memory cell array are precharged, the first precharge circuit and the second precharge circuit are deactivated, and data in the column switches in the one memory cell array is deactivated. Only the column switch corresponding to the memory cell to read is turned on, the n column switches in the other memory cell array are turned on, and the word line in the one memory cell array and the other memory cell array 4. The semiconductor memory device according to appendix 3, wherein the dummy word line is activated. .
(Appendix 5)
The two memory cell arrays are a first memory cell array and a second memory cell array,
A plurality of memory blocks including the first memory cell array, the second memory cell array, and the sense amplifier;
The common bit lines connected to the first memory cell array in each memory block are connected to each other via a first switch circuit and also connected to the second memory cell array in each memory block. The common bit lines are connected to each other via a second switch circuit;
When the dummy word line in the first memory cell array is activated, the control circuit sets the first switch circuit in a conductive state and the second switch circuit in a non-conductive state, The semiconductor memory device according to appendix 3 or 4, wherein when the dummy word line in the memory cell array is activated, the first switch circuit is turned off and the second switch circuit is turned on. .
(Appendix 6)
Each of the memory cell arrays is
A third switch circuit for short-circuiting each bit line;
The semiconductor according to any one of appendices 1 to 5, wherein when the dummy word line is activated, the control circuit short-circuits the bit lines by bringing the third switch circuit into a conductive state. Storage device.
(Appendix 7)
On the area of the memory cell in each memory cell array,
A first diffusion region;
The bit line formed on the first diffusion region and extending in a column direction;
A first contact connecting the first diffusion region and the bit line;
A first word line formed on the first diffusion region closer to the first direction than the first contact and extending in a row direction orthogonal to the column direction;
A second word line formed on the first diffusion region on the second direction side opposite to the first direction from the first contact and extending in the row direction;
A first power supply line formed on the first diffusion region closer to the first direction than the first word line and extending in the row direction;
A second power supply line formed on the first diffusion region on the second direction side than the second word line and extending in the row direction;
In the first diffusion region, the memory cells are respectively formed on the first direction side and the second direction side with the first contact as a center,
On the area of the dummy cell in each memory cell array,
A second diffusion region;
The bit line formed on the second diffusion region and extending in the column direction;
A second contact connecting the second diffusion region and the bit line;
A first dummy word line formed on the second diffusion region closer to the first direction than the second contact and extending in the row direction;
A second dummy word line formed on the second diffusion region closer to the second direction than the second contact and extending in the row direction;
A third power supply line formed on the second diffusion region on the first direction side of the first dummy word line and extending in the row direction;
A fourth power supply line formed on the second diffusion region on the second direction side than the second dummy word line and extending in the row direction;
In any one of Supplementary notes 1 to 6, wherein the dummy cells are formed in the second diffusion region on the first direction side and the second direction side, respectively, with the second contact as a center. The semiconductor memory device described.
(Appendix 8)
When reading data from one memory cell array, the control circuit activates the first dummy word line of the other memory cell array when the first word line of the one memory cell array is activated The semiconductor device according to appendix 7, wherein when the second word line of the one memory cell array is activated, the second dummy word line of the other memory cell array is activated. Storage device.
(Appendix 9)
When the control circuit reads data from one memory cell array, when one of the first word line and the second word line of the one memory cell array is activated, the other memory The semiconductor memory device according to appendix 7, wherein the first dummy word line and the second dummy word line of the cell array are activated.
(Appendix 10)
Two memory cell arrays, a sense amplifier shared by the two memory cell arrays, and a control circuit for controlling data reading from the two memory cell arrays,
Each of the memory cell arrays is
m word lines (m is an integer greater than or equal to 2), n (n is an integer greater than or equal to 2) bit lines, memory cells provided at the intersections of the bit lines and the word lines, and at least a part A dummy cell provided at an intersection of the bit line and the dummy word line,
When the control circuit reads data from one memory cell array, the control circuit activates the dummy word line of the other memory cell array and generates a latch signal for determining a latch timing in the sense amplifier by the dummy cell. A semiconductor memory device.
(Appendix 11)
m word lines (m is an integer greater than or equal to 2), n (n is an integer greater than or equal to 2) bit lines, memory cells provided at the intersections of the bit lines and the word lines, and at least a part A data read method for reading data from a semiconductor memory device having two memory cell arrays having dummy cells provided at intersections of the bit lines and dummy word lines, and a sense amplifier shared by the two memory cell arrays. And
A data read, wherein when data is read from one of the two memory cell arrays, the dummy word line of the other memory cell array is activated and a reference level of the sense amplifier is generated by the dummy cell Method.

1, 2, 3 Semiconductor memory device 10U, 10D, 12U, 12D Memory cell array 11 Precharge circuit 30 Sense amplifier 50 Control circuit MC Memory cell T1 Cell transistor DMC Dummy cell DT Dummy transistor BL0U to BL15U Bit line BL0D to BL15D Bit line WL0U to WLmU Word line WL0D to WLmD Word line DWLU, DWLU0, DWLU1 Dummy word line DWLD, DWLD0, DWLD1 Dummy word line DBU, DBD Data bit line DBU0 to DBU2 Data bit line DBD0 to DBD2 Data bit line SU, SD Column switch S2 Switch circuit S3 switch circuit G0 transfer gate G1 transfer gate MB0 to MB2 memory block AR diffusion area DAR diffusion area BCT1 Doo-line contact BCT2 bit line contact CT contacts

Claims (8)

m word lines (m is an integer greater than or equal to 2), n (n is an integer greater than or equal to 2) bit lines, memory cells provided at the intersections of the bit lines and the word lines, and at least a part Two memory cell arrays having dummy cells provided at intersections of the bit lines and dummy word lines ,
A sense amplifier shared by the two memory cell arrays;
A control circuit for controlling data reading from the two memory cell arrays;
N column switches each having one terminal connected to the n bit lines;
A common bit line to which the other terminals of the n column switches are connected in common;
The two memory cell arrays are a first memory cell array and a second memory cell array, and a plurality of memory blocks including the first memory cell array, the second memory cell array, and the sense amplifier, Have
The sense amplifier is connected to the common bit line of each memory cell array,
The common bit lines connected to the first memory cell array in each memory block are connected to each other via a first switch circuit and also connected to the second memory cell array in each memory block. The common bit lines are connected to each other via a second switch circuit;
The control circuit includes:
When data is read from one memory cell array, the column switch corresponding to the memory cell from which data is read out of the column switches in the one memory cell array and the n column switches in the other memory cell array are turned on. And control to activate the word line in the one memory cell array and the dummy word line in the other memory cell array to generate the reference level of the sense amplifier by the dummy cell ,
When activating the dummy word line in the first memory cell array, the first switch circuit is turned on and the second switch circuit is turned off, while the second memory cell array is turned off. A semiconductor memory device characterized in that when the dummy word line is activated, the first switch circuit is turned off and the second switch circuit is turned on . The memory cell is a cell transistor having a gate connected to the word line and a drain connected to the bit line,
The dummy cell is a replica transistor of the cell transistor having a gate connected to the dummy word line, a drain connected to the bit line, and a source grounded,
2. The semiconductor memory device according to claim 1, wherein the dummy cell is provided at an intersection of (n / 2) bit lines of the n bit lines and the dummy word line. A first precharge circuit for precharging each bit line to a predetermined potential;
A second precharge circuit for precharging the common bit line to the predetermined potential;
The control circuit activates the first precharge circuit and the second precharge circuit by turning on the n column switches in each memory cell array when reading data from one memory cell array. After the n bit lines of each memory cell array are precharged, the first precharge circuit and the second precharge circuit are deactivated, and data in the column switches in the one memory cell array is deactivated. Only the column switch corresponding to the memory cell to read is turned on, the n column switches in the other memory cell array are turned on, and the word line in the one memory cell array and the other memory cell array semiconductor according to claim 1 or 2, characterized in that activating said dummy word line Storage device. Each of the memory cell arrays is
A third switch circuit for short-circuiting each bit line;
The control circuit according to the any one of claims 1 to 3, characterized in that for short-circuiting the bit lines and the third switch circuit to a conductive state when activating said dummy word line Semiconductor memory device. On the area of the memory cell in each memory cell array,
A first diffusion region;
The bit line formed on the first diffusion region and extending in a column direction;
A first contact connecting the first diffusion region and the bit line;
A first word line formed on the first diffusion region closer to the first direction than the first contact and extending in a row direction orthogonal to the column direction;
A second word line formed on the first diffusion region on the second direction side opposite to the first direction from the first contact and extending in the row direction;
A first power supply line formed on the first diffusion region closer to the first direction than the first word line and extending in the row direction;
A second power supply line formed on the first diffusion region on the second direction side than the second word line and extending in the row direction;
In the first diffusion region, the memory cells are respectively formed on the first direction side and the second direction side with the first contact as a center,
On the area of the dummy cell in each memory cell array,
A second diffusion region;
The bit line formed on the second diffusion region and extending in the column direction;
A second contact connecting the second diffusion region and the bit line;
A first dummy word line formed on the second diffusion region closer to the first direction than the second contact and extending in the row direction;
A second dummy word line formed on the second diffusion region closer to the second direction than the second contact and extending in the row direction;
A third power supply line formed on the second diffusion region on the first direction side of the first dummy word line and extending in the row direction;
A fourth power supply line formed on the second diffusion region on the second direction side than the second dummy word line and extending in the row direction;
5. The dummy cell according to claim 1 , wherein the dummy cells are formed in the second diffusion region on the first direction side and the second direction side, respectively, with the second contact as a center. The semiconductor memory device described in 1. When reading data from one memory cell array, the control circuit activates the first dummy word line of the other memory cell array when the first word line of the one memory cell array is activated 6. The method according to claim 5 , wherein when the second word line of the one memory cell array is activated, the second dummy word line of the other memory cell array is activated. Semiconductor memory device. When the control circuit reads data from one memory cell array, when one of the first word line and the second word line of the one memory cell array is activated, the other memory 6. The semiconductor memory device according to claim 5 , wherein the first dummy word line and the second dummy word line of the cell array are activated. m word lines (m is an integer greater than or equal to 2), n (n is an integer greater than or equal to 2) bit lines, memory cells provided at the intersections of the bit lines and the word lines, and at least a part A data read method for reading data from a semiconductor memory device having two memory cell arrays having dummy cells provided at intersections of the bit lines and dummy word lines, and a sense amplifier shared by the two memory cell arrays. And
The semiconductor memory device
N column switches each having one terminal connected to the n bit lines;
A common bit line to which the other terminals of the n column switches are connected in common;
The two memory cell arrays are a first memory cell array and a second memory cell array, and a plurality of memory blocks including the first memory cell array, the second memory cell array, and the sense amplifier, Have
The sense amplifier is connected to the common bit line of each memory cell array,
The common bit lines connected to the first memory cell array in each memory block are connected to each other via a first switch circuit and also connected to the second memory cell array in each memory block. The common bit lines are connected to each other via a second switch circuit;
When reading data from one of the two memory cell arrays, a column switch corresponding to a memory cell from which data is read out of the column switch in the one memory cell array and the column switch in the other memory cell array. n column switches are turned on, the word lines in the one memory cell array and the dummy word lines in the other memory cell array are activated, and the reference level of the sense amplifier is generated by the dummy cells ;
When activating the dummy word line in the first memory cell array, the first switch circuit is turned on and the second switch circuit is turned off, while the second memory cell array is turned off. A data reading method characterized in that when the dummy word line is activated, the first switch circuit is turned off and the second switch circuit is turned on .

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