IN2012DN02104A - - Google Patents

Download PDF

Info

Publication number
IN2012DN02104A
IN2012DN02104A IN2104DEN2012A IN2012DN02104A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A IN 2104DEN2012 A IN2104DEN2012 A IN 2104DEN2012A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A
Authority
IN
India
Prior art keywords
user
processor core
level interrupt
application thread
thread executing
Prior art date
Application number
Other languages
English (en)
Inventor
Jaewoong Chung
Karin Strauss
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02104A publication Critical patent/IN2012DN02104A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/16—Arrangements for providing special services to substations
    • H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
    • H04L12/1881—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast with schedule organisation, e.g. priority, sequence management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
IN2104DEN2012 2009-08-14 2010-08-05 IN2012DN02104A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23398309P 2009-08-14 2009-08-14
US12/633,007 US8255603B2 (en) 2009-08-14 2009-12-08 User-level interrupt mechanism for multi-core architectures
US12/633,034 US8285904B2 (en) 2009-08-14 2009-12-08 Flexible notification mechanism for user-level interrupts
US12/633,032 US8356130B2 (en) 2009-08-14 2009-12-08 Mechanism for recording undeliverable user-level interrupts
PCT/US2010/044528 WO2011019578A1 (en) 2009-08-14 2010-08-05 User-level interrupt mechanism for multi-core architectures

Publications (1)

Publication Number Publication Date
IN2012DN02104A true IN2012DN02104A (ko) 2015-08-21

Family

ID=43589266

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2104DEN2012 IN2012DN02104A (ko) 2009-08-14 2010-08-05

Country Status (7)

Country Link
US (3) US8255603B2 (ko)
EP (1) EP2465032B1 (ko)
JP (1) JP5646628B2 (ko)
KR (1) KR101651246B1 (ko)
CN (1) CN102483705B (ko)
IN (1) IN2012DN02104A (ko)
WO (1) WO2011019578A1 (ko)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009134217A1 (en) * 2008-04-28 2009-11-05 Hewlett-Packard Development Company, L.P. Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems
US8255603B2 (en) * 2009-08-14 2012-08-28 Advanced Micro Devices, Inc. User-level interrupt mechanism for multi-core architectures
US8566492B2 (en) * 2009-12-31 2013-10-22 Intel Corporation Posting interrupts to virtual processors
US9652365B2 (en) * 2010-08-24 2017-05-16 Red Hat, Inc. Fault configuration using a registered list of controllers
KR101717494B1 (ko) * 2010-10-08 2017-03-28 삼성전자주식회사 인터럽트 처리 장치 및 방법
US8370283B2 (en) * 2010-12-15 2013-02-05 Scienergy, Inc. Predicting energy consumption
WO2012082556A2 (en) 2010-12-15 2012-06-21 Advanced Micro Devices, Inc. Computer system interrupt handling
WO2013057769A1 (ja) * 2011-10-20 2013-04-25 富士通株式会社 情報処理装置、情報処理装置の制御方法および制御プログラム
CN102520916B (zh) * 2011-11-28 2015-02-11 深圳中微电科技有限公司 在mvp处理器中消除纹理延迟和寄存器管理的方法
WO2013100948A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Delivering real time interrupts with an advanced programmable interrupt controller
KR101331957B1 (ko) * 2012-01-11 2013-11-21 엘아이지넥스원 주식회사 범용 운영체제의 실시간성 쓰레드 처리를 위한 커널 구성 방법
US9785133B2 (en) * 2012-02-10 2017-10-10 Fisher-Rosemount Systems, Inc. Methods for collaboratively assisting a control room operator
US8849731B2 (en) * 2012-02-23 2014-09-30 Microsoft Corporation Content pre-fetching for computing devices
US9043522B2 (en) 2012-10-17 2015-05-26 Arm Limited Handling interrupts in a multi-processor system
US9208113B2 (en) 2013-01-15 2015-12-08 Apple Inc. Deferred inter-processor interrupts
US9495311B1 (en) * 2013-12-17 2016-11-15 Google Inc. Red zone avoidance for user mode interrupts
US9594704B1 (en) 2013-12-17 2017-03-14 Google Inc. User mode interrupts
US9674141B2 (en) * 2013-12-27 2017-06-06 Intel Corporation Techniques for implementing a secure mailbox in resource-constrained embedded systems
US9563588B1 (en) 2014-01-29 2017-02-07 Google Inc. OS bypass inter-processor interrupt delivery mechanism
US9542254B2 (en) 2014-07-30 2017-01-10 International Business Machines Corporation Application-level signal handling and application-level memory protection
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
KR102187912B1 (ko) 2014-09-26 2020-12-07 인텔 코포레이션 인터럽트들의 세트들을 구성하는 장치 및 방법
US9910699B2 (en) 2014-10-28 2018-03-06 Intel Corporation Virtual processor direct interrupt delivery mechanism
US9928094B2 (en) * 2014-11-25 2018-03-27 Microsoft Technology Licensing, Llc Hardware accelerated virtual context switching
US9921984B2 (en) * 2014-12-23 2018-03-20 Intel Corporation Delivering interrupts to user-level applications
US10002103B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10002102B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10922252B2 (en) * 2015-06-22 2021-02-16 Qualcomm Incorporated Extended message signaled interrupts (MSI) message data
CN105094976A (zh) * 2015-10-09 2015-11-25 天津国芯科技有限公司 一种中断控制方法和中断控制器
CN105808338A (zh) * 2016-03-17 2016-07-27 李晓波 一种在处理中实现中断响应核可配置的方法及装置
CN107800546B (zh) 2016-08-31 2021-03-30 华为技术有限公司 一种广播消息的管理方法及装置
US10496572B1 (en) 2017-03-06 2019-12-03 Apple Inc. Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled
US10467162B2 (en) * 2017-03-31 2019-11-05 Hewlett Packard Enterprise Development Lp Interrupt based on a last interrupt request indicator and a work acknowledgement
US10838760B2 (en) * 2017-11-29 2020-11-17 Nxp Usa, Inc. Systems and methods for interrupt distribution
CN112470125B (zh) * 2018-07-24 2024-02-20 三菱电机株式会社 中断处理方法、计算机系统以及存储介质
TWI703501B (zh) * 2018-08-23 2020-09-01 慧榮科技股份有限公司 具有分散式信箱架構的多處理器系統及其溝通方法
US11372711B2 (en) 2019-06-29 2022-06-28 Intel Corporation Apparatus and method for fault handling of an offload transaction
US11182208B2 (en) 2019-06-29 2021-11-23 Intel Corporation Core-to-core start “offload” instruction(s)
US11321144B2 (en) 2019-06-29 2022-05-03 Intel Corporation Method and apparatus for efficiently managing offload work between processing units
US11366769B1 (en) * 2021-02-25 2022-06-21 Microsoft Technology Licensing, Llc Enabling peripheral device messaging via application portals in processor-based devices
US20230099517A1 (en) * 2021-09-30 2023-03-30 Intel Corporation User-level interprocessor interrupts
US20230315659A1 (en) * 2022-03-29 2023-10-05 Mellanox Technologies, Ltd. Interrupt emulation on network devices

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05189252A (ja) * 1992-01-13 1993-07-30 Meidensha Corp ソフトウェアのイベント処理方法
US5909582A (en) * 1996-04-26 1999-06-01 Nec Corporation Microcomputer having user mode interrupt function and supervisor mode interrupt function
US6061709A (en) * 1998-07-31 2000-05-09 Integrated Systems Design Center, Inc. Integrated hardware and software task control executive
US6370606B1 (en) 1998-11-05 2002-04-09 Compaq Computer Corporation System and method for simulating hardware interrupts in a multiprocessor computer system
US6148361A (en) * 1998-12-17 2000-11-14 International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
JP4057769B2 (ja) * 2000-08-31 2008-03-05 松下電器産業株式会社 割り込み管理装置及び割り込み管理方法
US7529235B2 (en) * 2000-12-06 2009-05-05 Franklin Zhigang Zhang Internet based time distributed message network system and personal mobile access device
US7392282B2 (en) * 2001-03-14 2008-06-24 International Business Machines Corporation Method for ensuring client access to messages from a server
JP2005190207A (ja) * 2003-12-25 2005-07-14 Matsushita Electric Ind Co Ltd 割り込み制御装置、制御方法
GB0404696D0 (en) 2004-03-02 2004-04-07 Level 5 Networks Ltd Dual driver interface
US7080179B1 (en) * 2004-03-26 2006-07-18 Foundry Networks, Inc. Multi-level interrupts
US9189230B2 (en) 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US7689747B2 (en) * 2005-03-28 2010-03-30 Microsoft Corporation Systems and methods for an augmented interrupt controller and synthetic interrupt sources
US7581051B2 (en) * 2005-05-16 2009-08-25 Microsoft Corporation Method for delivering interrupts to user mode drivers
US20070073928A1 (en) 2005-09-26 2007-03-29 John Bruno High-speed input/output signaling mechanism using a polling CPU and cache coherency signaling
US7493436B2 (en) * 2006-10-26 2009-02-17 International Business Machines Corporation Interrupt handling using simultaneous multi-threading
US8689215B2 (en) * 2006-12-19 2014-04-01 Intel Corporation Structured exception handling for application-managed thread units
US7627706B2 (en) * 2007-09-06 2009-12-01 Intel Corporation Creation of logical APIC ID with cluster ID and intra-cluster ID
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US8255603B2 (en) 2009-08-14 2012-08-28 Advanced Micro Devices, Inc. User-level interrupt mechanism for multi-core architectures

Also Published As

Publication number Publication date
US8285904B2 (en) 2012-10-09
US20110040913A1 (en) 2011-02-17
US20110040914A1 (en) 2011-02-17
EP2465032A1 (en) 2012-06-20
EP2465032B1 (en) 2020-12-16
JP2013502004A (ja) 2013-01-17
US20110040915A1 (en) 2011-02-17
WO2011019578A1 (en) 2011-02-17
KR101651246B1 (ko) 2016-09-05
US8255603B2 (en) 2012-08-28
CN102483705A (zh) 2012-05-30
KR20120062768A (ko) 2012-06-14
US8356130B2 (en) 2013-01-15
CN102483705B (zh) 2014-12-17
JP5646628B2 (ja) 2014-12-24

Similar Documents

Publication Publication Date Title
IN2012DN02104A (ko)
GB2520852A (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
WO2011115984A3 (en) Pluggable token provider model to implement authentication across multiple web services
WO2012033839A3 (en) Oxygen concentrator heat management system and method
WO2010101788A3 (en) Access control using identifiers in links
BR112014013644A2 (pt) método de realização de agente de serviço de nuvem; servidor de agente de serviço de nuvem; e sistema de realização do agente de serviço de nuvem
IN2012CN07526A (ko)
MY181023A (en) Conversational message service operating method for providing acknowledgement
MX2013014175A (es) Metodos y aparatos para restauracion desde multiples fuentes.
MX2013009839A (es) Acceso de espera para abastecimiento compartido en energia.
IN2015DN02657A (ko)
WO2010068356A3 (en) System and method for communicating over a network with a medical device
GB201219578D0 (en) System and control method
WO2013089782A3 (en) Co-location electrical architecture
HK1166405A1 (zh) 用於基於狀態消息的上下文相關廣告的系統和方法
EP2383946A4 (en) METHOD, SERVER AND SYSTEM FOR SUPPLYING RESOURCES TO AN ACCESS USER
MX337872B (es) Integridad de cadenas de mensajes.
GB2520858A (en) Instruction set for message scheduling of SHA256 algorithm
MX2012000392A (es) Servicio de agregacion de informacion.
EP2773073A4 (en) INPUT GENERATING METHOD, MESSAGE RECEIVING METHOD, AND CORRESPONDING DEVICE AND SYSTEM
WO2010043706A3 (fr) Procede d'execution deterministe et de synchronisation d'un systeme de traitement de l'information comportant plusieurs coeurs de traitement executant des taches systemes
SG11201402442UA (en) A method of generation and transmission of secure tokens based on tokens generated by trng and split into shares and the system thereof
AR081035A1 (es) Aparato receptor, metodo de control de anuncio, y programa
IN2012DN03242A (ko)
IN2013CH04831A (ko)