IN190505B - - Google Patents

Info

Publication number
IN190505B
IN190505B IN2070CA1996A IN190505B IN 190505 B IN190505 B IN 190505B IN 2070CA1996 A IN2070CA1996 A IN 2070CA1996A IN 190505 B IN190505 B IN 190505B
Authority
IN
India
Prior art keywords
memory cells
word lines
erasing
eeprom
memory
Prior art date
Application number
Other languages
English (en)
Inventor
Holger Sedlak
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IN190505B publication Critical patent/IN190505B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Electrotherapy Devices (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
IN2070CA1996 1995-12-06 1996-12-02 IN190505B (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19545523A DE19545523C2 (de) 1995-12-06 1995-12-06 EEPROM und Verfahren zur Ansteuerung desselben

Publications (1)

Publication Number Publication Date
IN190505B true IN190505B (fr) 2003-08-02

Family

ID=7779359

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2070CA1996 IN190505B (fr) 1995-12-06 1996-12-02

Country Status (6)

Country Link
EP (2) EP1191541B1 (fr)
AT (2) ATE222020T1 (fr)
DE (3) DE19545523C2 (fr)
ES (2) ES2215838T3 (fr)
IN (1) IN190505B (fr)
WO (1) WO1997021224A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5033023A (en) * 1988-04-08 1991-07-16 Catalyst Semiconductor, Inc. High density EEPROM cell and process for making the cell
JP2807256B2 (ja) * 1989-03-17 1998-10-08 株式会社東芝 不揮発性半導体メモリ
US5065364A (en) * 1989-09-15 1991-11-12 Intel Corporation Apparatus for providing block erasing in a flash EPROM
JP2632104B2 (ja) * 1991-11-07 1997-07-23 三菱電機株式会社 不揮発性半導体記憶装置
EP0637035B1 (fr) * 1993-07-29 1996-11-13 STMicroelectronics S.r.l. Structure de circuit pour matrice de mémoire et procédé de fabrication y reférant

Also Published As

Publication number Publication date
ES2181934T3 (es) 2003-03-01
DE19545523A1 (de) 1997-06-26
EP0808500B1 (fr) 2002-08-07
WO1997021224A3 (fr) 1997-08-07
EP1191541B1 (fr) 2004-02-11
WO1997021224A2 (fr) 1997-06-12
DE19545523C2 (de) 2001-02-15
ES2215838T3 (es) 2004-10-16
EP1191541A2 (fr) 2002-03-27
ATE259536T1 (de) 2004-02-15
DE59609541D1 (de) 2002-09-12
EP0808500A2 (fr) 1997-11-26
EP1191541A3 (fr) 2002-08-14
DE59610916D1 (de) 2004-03-18
ATE222020T1 (de) 2002-08-15

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