ES2181934T3 - Eeprom y procedimiento para la activacion de la misma. - Google Patents

Eeprom y procedimiento para la activacion de la misma.

Info

Publication number
ES2181934T3
ES2181934T3 ES96946005T ES96946005T ES2181934T3 ES 2181934 T3 ES2181934 T3 ES 2181934T3 ES 96946005 T ES96946005 T ES 96946005T ES 96946005 T ES96946005 T ES 96946005T ES 2181934 T3 ES2181934 T3 ES 2181934T3
Authority
ES
Spain
Prior art keywords
memory cells
eeprom
word lines
erasing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES96946005T
Other languages
English (en)
Inventor
Holger Sedlak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of ES2181934T3 publication Critical patent/ES2181934T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Electrotherapy Devices (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

SE DESCRIBE UNA EEPROM CON MULTITUD DE POSICIONES DE MEMORIA DISPUESTAS EN UN CAMPO DE POSICIONES DE MEMORIA, QUE SE PUEDEN OPERAR PARA ESCRITURA, LECTURA Y BORRADO MEDIANTE HILOS DE PALABRA, BIT Y FUENTE (WL, BL, SL). LA EEPROM DESCRITA SE CARACTERIZA PORQUE LAS POSICIONES DE MEMORIA OPERABLES POR UN HILO DE PALABRA INDIVIDUAL (WL) SE DIVIDE EN NUMEROSOS GRUPOS, A CADA UNO DE LOS CUALES SE ASIGNA UN HILO DE FUENTE COMUN (SL). EL PROCEDIMIENTO PARA LA ACTIVACION DE LA EEPROM SE CARACTERIZA PORQUE SE REALIZA POR GRUPOS LA ESCRITURA, LECTURA O BORRADO DE LAS POSICIONES DE MEMORIA OPERABLES POR UN HILO DE PALABRA (WL) INDIVIDUAL.
ES96946005T 1995-12-06 1996-11-21 Eeprom y procedimiento para la activacion de la misma. Expired - Lifetime ES2181934T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19545523A DE19545523C2 (de) 1995-12-06 1995-12-06 EEPROM und Verfahren zur Ansteuerung desselben

Publications (1)

Publication Number Publication Date
ES2181934T3 true ES2181934T3 (es) 2003-03-01

Family

ID=7779359

Family Applications (2)

Application Number Title Priority Date Filing Date
ES01127740T Expired - Lifetime ES2215838T3 (es) 1995-12-06 1996-11-21 Eeprom y procedimiento para la activacion de la misma.
ES96946005T Expired - Lifetime ES2181934T3 (es) 1995-12-06 1996-11-21 Eeprom y procedimiento para la activacion de la misma.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
ES01127740T Expired - Lifetime ES2215838T3 (es) 1995-12-06 1996-11-21 Eeprom y procedimiento para la activacion de la misma.

Country Status (6)

Country Link
EP (2) EP0808500B1 (es)
AT (2) ATE259536T1 (es)
DE (3) DE19545523C2 (es)
ES (2) ES2215838T3 (es)
IN (1) IN190505B (es)
WO (1) WO1997021224A2 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5033023A (en) * 1988-04-08 1991-07-16 Catalyst Semiconductor, Inc. High density EEPROM cell and process for making the cell
JP2807256B2 (ja) * 1989-03-17 1998-10-08 株式会社東芝 不揮発性半導体メモリ
US5065364A (en) * 1989-09-15 1991-11-12 Intel Corporation Apparatus for providing block erasing in a flash EPROM
JP2632104B2 (ja) * 1991-11-07 1997-07-23 三菱電機株式会社 不揮発性半導体記憶装置
EP0637035B1 (en) * 1993-07-29 1996-11-13 STMicroelectronics S.r.l. Circuit structure for a memory matrix and corresponding manufacturing method

Also Published As

Publication number Publication date
DE19545523C2 (de) 2001-02-15
EP1191541A3 (de) 2002-08-14
DE59610916D1 (de) 2004-03-18
EP1191541B1 (de) 2004-02-11
EP0808500B1 (de) 2002-08-07
EP0808500A2 (de) 1997-11-26
DE59609541D1 (de) 2002-09-12
DE19545523A1 (de) 1997-06-26
WO1997021224A3 (de) 1997-08-07
ATE259536T1 (de) 2004-02-15
EP1191541A2 (de) 2002-03-27
ATE222020T1 (de) 2002-08-15
ES2215838T3 (es) 2004-10-16
IN190505B (es) 2003-08-02
WO1997021224A2 (de) 1997-06-12

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