IN170464B - - Google Patents

Info

Publication number
IN170464B
IN170464B IN121/DEL/87A IN121DE1987A IN170464B IN 170464 B IN170464 B IN 170464B IN 121DE1987 A IN121DE1987 A IN 121DE1987A IN 170464 B IN170464 B IN 170464B
Authority
IN
India
Application number
IN121/DEL/87A
Other languages
English (en)
Inventor
Paul James Natusch
Eugene Lay Yu
David Carmine Senerchia
John Frederick Henry
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of IN170464B publication Critical patent/IN170464B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
IN121/DEL/87A 1986-01-29 1987-02-13 IN170464B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82368786A 1986-01-29 1986-01-29

Publications (1)

Publication Number Publication Date
IN170464B true IN170464B (sv) 1992-03-28

Family

ID=25239418

Family Applications (1)

Application Number Title Priority Date Filing Date
IN121/DEL/87A IN170464B (sv) 1986-01-29 1987-02-13

Country Status (12)

Country Link
EP (1) EP0288479B1 (sv)
JP (1) JPH01501346A (sv)
KR (1) KR910005379B1 (sv)
CN (1) CN1007186B (sv)
AU (1) AU6931087A (sv)
CA (1) CA1286412C (sv)
DE (1) DE3785191D1 (sv)
ES (1) ES2004078A6 (sv)
IL (1) IL81427A (sv)
IN (1) IN170464B (sv)
MX (1) MX168581B (sv)
WO (1) WO1987004825A1 (sv)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1324679C (en) * 1989-02-03 1993-11-23 Michael A. Gagliardo Method and means for interfacing a system control unit for a multi-processor system with the system main memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
DE2537787A1 (de) * 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4451880A (en) * 1980-10-31 1984-05-29 Honeywell Information Systems Inc. Memory controller with interleaved queuing apparatus
JPS58215777A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd 記憶制御方式

Also Published As

Publication number Publication date
CN87102176A (zh) 1987-09-02
EP0288479B1 (en) 1993-03-31
MX168581B (es) 1993-06-01
KR880700973A (ko) 1988-04-13
JPH01501346A (ja) 1989-05-11
IL81427A (en) 1991-06-10
DE3785191D1 (de) 1993-05-06
CN1007186B (zh) 1990-03-14
IL81427A0 (en) 1987-08-31
EP0288479A1 (en) 1988-11-02
ES2004078A6 (es) 1988-12-01
AU6931087A (en) 1987-08-25
WO1987004825A1 (en) 1987-08-13
KR910005379B1 (ko) 1991-07-29
CA1286412C (en) 1991-07-16

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