Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/52—Multiplying; Dividing
  • G06F7/523—Multiplying only
  • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
  • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
  • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
  • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computational Mathematics (AREA)
• Mathematical Analysis (AREA)
• Mathematical Optimization (AREA)
• Pure & Applied Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Complex Calculations (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=20668226

Family Applications (1)

Country Status (10)

Families Citing this family (2)

• 1976
  • 1976-07-07 SU SU762379678A patent/SU651341A1/ru active
• 1977
  • 1977-07-06 IN IN1026/CAL/77A patent/IN147436B/en unknown
  • 1977-07-06 DD DD19992377A patent/DD131420A1/xx unknown
  • 1977-07-07 DE DE19772730793 patent/DE2730793A1/de not_active Ceased
  • 1977-07-07 FR FR7720935A patent/FR2357958A1/fr active Granted
  • 1977-07-07 BG BG7736825A patent/BG29702A1/xx unknown
  • 1977-07-07 JP JP8049277A patent/JPS5317043A/ja active Pending
  • 1977-07-07 PL PL19944977A patent/PL108592B1/pl not_active IP Right Cessation
  • 1977-07-07 RO RO7790966A patent/RO80742A/ro unknown
  • 1977-07-07 GB GB2860577A patent/GB1540945A/en not_active Expired

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