IN147436B - - Google Patents

Info

Publication number
IN147436B
IN147436B IN1026/CAL/77A IN1026CA1977A IN147436B IN 147436 B IN147436 B IN 147436B IN 1026CA1977 A IN1026CA1977 A IN 1026CA1977A IN 147436 B IN147436 B IN 147436B
Authority
IN
India
Application number
IN1026/CAL/77A
Other languages
English (en)
Inventor
Mansur Zakirovich Shagivaleev
Valery Fedorovich Gusev
Jury Ivanovich Schetinin
Vladimir Yakovlevich Kontarev
Vyacheslav Yakovlevich Kremlev
Gennady Nikolaevich Ivanov
Azat Usmanovich Yarmukhametov
Genrikh Isaevich Krengel
Original Assignee
Shagivaleev Mansur Z
Gusev Valery
Schetinin Jury I
Kontarev Vladimir Ya
Kremlev V J
Ivanov Gennadij N
Jarmuchametov Azat U
Krengel Genrikh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shagivaleev Mansur Z, Gusev Valery, Schetinin Jury I, Kontarev Vladimir Ya, Kremlev V J, Ivanov Gennadij N, Jarmuchametov Azat U, Krengel Genrikh filed Critical Shagivaleev Mansur Z
Publication of IN147436B publication Critical patent/IN147436B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
IN1026/CAL/77A 1976-07-07 1977-07-06 IN147436B (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762379678A SU651341A1 (ru) 1976-07-07 1976-07-07 Устройство дл умножени

Publications (1)

Publication Number Publication Date
IN147436B true IN147436B (pl) 1980-02-23

Family

ID=20668226

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1026/CAL/77A IN147436B (pl) 1976-07-07 1977-07-06

Country Status (10)

Country Link
JP (1) JPS5317043A (pl)
BG (1) BG29702A1 (pl)
DD (1) DD131420A1 (pl)
DE (1) DE2730793A1 (pl)
FR (1) FR2357958A1 (pl)
GB (1) GB1540945A (pl)
IN (1) IN147436B (pl)
PL (1) PL108592B1 (pl)
RO (1) RO80742A (pl)
SU (1) SU651341A1 (pl)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334284A (en) * 1979-12-31 1982-06-08 Sperry Corporation Multiplier decoding using parallel MQ register
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit

Also Published As

Publication number Publication date
PL199449A1 (pl) 1978-03-28
RO80742A (ro) 1983-06-01
FR2357958B1 (pl) 1980-03-07
SU651341A1 (ru) 1979-03-05
DE2730793A1 (de) 1978-01-19
FR2357958A1 (fr) 1978-02-03
GB1540945A (en) 1979-02-21
PL108592B1 (en) 1980-04-30
BG29702A1 (en) 1981-01-15
DD131420A1 (de) 1978-06-21
RO80742B (ro) 1983-05-30
JPS5317043A (en) 1978-02-16

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