IL95192A - מעבד רשת סנכרוני פשות - Google Patents

מעבד רשת סנכרוני פשות

Info

Publication number
IL95192A
IL95192A IL9519290A IL9519290A IL95192A IL 95192 A IL95192 A IL 95192A IL 9519290 A IL9519290 A IL 9519290A IL 9519290 A IL9519290 A IL 9519290A IL 95192 A IL95192 A IL 95192A
Authority
IL
Israel
Prior art keywords
processor
bit
processors
logic
array
Prior art date
Application number
IL9519290A
Other languages
English (en)
Other versions
IL95192A0 (en
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of IL95192A0 publication Critical patent/IL95192A0/xx
Publication of IL95192A publication Critical patent/IL95192A/he

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)
IL9519290A 1989-07-28 1990-07-26 מעבד רשת סנכרוני פשות IL95192A (he)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US38693389A 1989-07-28 1989-07-28

Publications (2)

Publication Number Publication Date
IL95192A0 IL95192A0 (en) 1991-06-10
IL95192A true IL95192A (he) 1994-02-27

Family

ID=23527699

Family Applications (1)

Application Number Title Priority Date Filing Date
IL9519290A IL95192A (he) 1989-07-28 1990-07-26 מעבד רשת סנכרוני פשות

Country Status (7)

Country Link
US (1) US5379444A (he)
EP (1) EP0410435A3 (he)
JP (1) JP2562845B2 (he)
KR (1) KR940000293B1 (he)
AU (1) AU624524B2 (he)
CA (1) CA2021192A1 (he)
IL (1) IL95192A (he)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
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US5692135A (en) * 1995-12-14 1997-11-25 International Business Machines Corporation Method and system for performing an asymmetric bus arbitration protocol within a data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) * 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
JP3961028B2 (ja) * 1996-12-27 2007-08-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データフロープロセッサ（ｄｆｐ）の自動的なダイナミックアンロード方法並びに２次元または３次元のプログラミング可能なセルストラクチャを有するモジュール（ｆｐｇａ，ｄｐｇａ等）
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
FR2778764B1 (fr) * 1998-05-15 2001-01-05 France Etat Procede de commande d'un reseau de processeurs
US6161161A (en) * 1999-01-08 2000-12-12 Cisco Technology, Inc. System and method for coupling a local bus to a peripheral component interconnect (PCI) bus
WO2000077652A2 (de) * 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequenz-partitionierung auf zellstrukturen
US6578133B1 (en) * 2000-02-24 2003-06-10 Stanley M. Hyduke MIMD array of single bit processors for processing logic equations in strict sequential order
EP2226732A3 (de) * 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
ATE437476T1 (de) 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
EP1402382B1 (de) * 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7376811B2 (en) * 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
US7577822B2 (en) * 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
EP1470478A2 (en) * 2002-01-18 2004-10-27 PACT XPP Technologies AG Method and device for partitioning large computer programs
DE10392560D2 (de) * 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
DE10390689D2 (de) 2002-02-18 2005-02-10 Pact Xpp Technologies Ag Bussysteme und Rekonfigurationsverfahren
WO2003081454A2 (de) * 2002-03-21 2003-10-02 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US8914590B2 (en) * 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2004021176A2 (de) * 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) * 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US20110238948A1 (en) * 2002-08-07 2011-09-29 Martin Vorbach Method and device for coupling a data processing unit and a data processing array
AU2003289844A1 (en) * 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP2006524850A (ja) * 2003-04-04 2006-11-02 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データ処理方法およびデータ処理装置
DE602004024995D1 (de) * 2003-05-23 2010-02-25 Nippon Telegraph & Telephone Parallelverarbeitungseinrichtung und parallelverarbeitungsverfahren
EP1676208A2 (en) * 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
EP1849095B1 (en) * 2005-02-07 2013-01-02 Richter, Thomas Low latency massive parallel data processing device
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US8656143B2 (en) 2006-03-13 2014-02-18 Laurence H. Cooke Variable clocked heterogeneous serial array processor
US20070226455A1 (en) * 2006-03-13 2007-09-27 Cooke Laurence H Variable clocked heterogeneous serial array processor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699534A (en) * 1970-12-15 1972-10-17 Us Navy Cellular arithmetic array
GB1536933A (en) * 1977-03-16 1978-12-29 Int Computers Ltd Array processors
US4380046A (en) * 1979-05-21 1983-04-12 Nasa Massively parallel processor computer
US4314349A (en) * 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4507748A (en) * 1982-08-02 1985-03-26 International Telephone And Telegraph Corporation Associative processor with variable length fast multiply capability
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4709327A (en) * 1983-05-31 1987-11-24 Hillis W Daniel Parallel processor/memory circuit
GB8517376D0 (en) * 1985-07-09 1985-08-14 Jesshope C R Processor array
CN1012297B (zh) * 1985-11-13 1991-04-03 奥尔凯托N·V公司 具有内部单元控制和处理的阵列结构
US4907148A (en) * 1985-11-13 1990-03-06 Alcatel U.S.A. Corp. Cellular array processor with individual cell-level data-dependent cell control and multiport input memory

Also Published As

Publication number Publication date
KR940000293B1 (ko) 1994-01-14
EP0410435A3 (en) 1992-02-26
JPH0370064A (ja) 1991-03-26
IL95192A0 (en) 1991-06-10
CA2021192A1 (en) 1991-01-29
AU5993090A (en) 1991-01-31
EP0410435A2 (en) 1991-01-30
AU624524B2 (en) 1992-06-11
US5379444A (en) 1995-01-03
JP2562845B2 (ja) 1996-12-11
KR910003515A (ko) 1991-02-27

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