IL43468A - Insertion of control signals and the like into time division multiplex pulse trains - Google Patents

Claims (6)

¾3¾68/2 WHAT IS CLAIMED ISt

1. · Process for inserting at the sending end binary signals into a sequence of time-multiplex signals· which said binary signals are received over individual feeders associated to communication channels characterized by the fact that the feeders are connected to gate circuits (τ) being individually situated at each Junction between columns (SL) and rows (ZL) of a switching matrix (s), that furthermore impulses derived from the pulse frame, fiequency are led to . the columns (SL) and that upon appearance of such an impulse at a column (SL). the signal-ization impulses appearing at the gate circuits (T.TA) of the corresponding column (SL) are led across the rows (ZL) to para Ilei -ieries, fioret//t( - ■Jcr-Zes aerlos- a»a1lei converter (w) and that this -series-parallel converter (w) is controlled for the purpose of insertin the sign&lization impulses provided by the rows (ZL) in a series sequence into the corresponding signallzatlon time compartment of. the corresponding pulse frame, by the time-multiplex signal >1 frequency (BT ) and at least one auxiliary frequency (ΗΓ) which | is in phase shift with respect to the v pulse frame frequency* ·!

2. Circuit for the implementation of the process according to Claim 1, characterized by the fact that a switching matri (s) is provide with individual gate circuits (τ) at the ' ,!." . . . . . . . . Junctions between columns (SL>) and rows (ZL) in such a manner that one input of the gate circuit (τ) is connected to the respective feeder (ZB), a second input toihe respective column (SL)( and ite output Is connected to the respective row (ZL), that furthermore, a decoder (TV) is provided which is controlled by fractions of the pulse frame frequency and which i turn controls one after the other the columne (SL) of the switching matr (S) connected to it through the individual gate circuits (τ) of the feeders. ■

3. · Circuit according to Claim 2, further characterized by the fact that the Individual gate circuitβ (τ) consist o logical AMD-circuitβ which provide an overvoltage limit (u) at the input connected to the respective feeder (ZB).

4. Circuit according to Claim 3 for inary signalization impulses,in which one signal position is defined by an earth potential applied to the far end of a feeder (ZB) and which may differ from the earth potential available at the switching matrix (s)f and the other signal position is defined by an open feeder at the far end, characterized by the fact that each gate circuit (T) of the switching matrix (S) is provided at its input end with a voltage divider (SV) consisting of three resistances (R1,R2,R3). its first tap connected to the respective feeder (ZB), its second tap "da a first diode to the/respective column (SC) and via a second diode to the respective row (ZL) that the end at the side of the first tap of the voltage divider (SW) is permanently connected to a first voltage (Ul) and the other end of the voltage divider (sw) is permanently. connected to a second voltage (U2) opposed in direction to the first voltage (Ul) and that the voltage difference between the first and the second voltage is larger than the largest voltage occuring on the feeder (ZB),

5. Circuit according to Claim 3» characterized by the fact that the overvoltage limiter (u) consistin of a condenser (c) and a voltage dependent variable resistance (RV) connected in parallel to the condenser (C) which is connected bvtweeii each feeder (ZB) and a terminal of the mains voltage*

6. Circuit according to Claim 3. further characterized Vy the fact that each column (SL) is provided with a power gate (TL) for amplification of the impulse applied to the column (SL).