GB964710A - Improvements in or relating to electrical signalling systems - Google Patents

Abstract

964,710. Multiple pulse signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Feb. 16, 1962 [Feb. 23, 1961], No. 6706/61. Heading H4L. In an arrangement for interconnecting two time division multiplex pulse systems controlled by respective timing signals which are independent but nominally of the same frequency, and subject to long term drift, wherein to facilitate the connection of channels of the first system to channels of the second system in a different time sequence the signals are stored at the interconnecting point, when the phase relationship between the interconnected channels reaches a point such that the storage time approaches zero, automatic control equipment introduces a temporary change in the storage period. Fig. 1 shows an arrangement for interconnecting systems A and B in which each system provides twenty-five channels, each channel involving eight digits, and channel twenty-five being the synchronizing channel. The A system is controlled by digit clock DA controlled by pulses derived from the incoming signal and producing pulses DA1 to DA8 corresponding to the digits for a channel and by channel clock CA driven by clock DA and producing pulses CA0 to CA24, in which CA0 relates to the synchronizing channel. Phasesynchronizing circuits may be included. Similarly, system B is controlled by digit clock DB and channel clock CB. The incoming pulse cede modulation signals from A are fed via a regenerative repeater RRR to gates G1, G2, controlled by pulses from a toggle T1 so that when one gate is open the other is closed. The gate G1 is connected through a three-bit delay D1 to the gates CA1 to CA24 controlled by the channel timing pulses, and the gate G2 is connected direct to the gates CA1 to CA24, and thus pulse signals are passed to the stores S. No store is provided for the synchronizing channel since synchronizing signals now are provided by the system B. A store S, Fig. 2, comprises capacitors C1 to C8 supplied via gates GDA controlled by digit timing pulses DA1 to DA8. The stored information is read out via digit gates GDB controlled by digit clock DB and gate channel gate GCB controlled by channel clock CB. The gates, GCB are operable in a variable sequence to provide the required cross-connection of channels. Any two interconnected A and B channels will drift slowly in and out of phase with the drift of their respective timing signals and to ensure adequate storage time to avoid loss of signals it is necessary to prevent them from going into phase as by the introduction of 3-digit delay D1 each time the in-phase condition is approached, the DA clock being altered correspondingly. The required switching may be carried out by comparing the synchronizing channel C0 digit positions of system A with those of any channel in the B system to operate toggle T1 through appropriate gate circuits, Fig. 6 (not shown). Specification 960,388 is referred to.