IL163526A0 - Electronic circuits - Google Patents

Electronic circuits

Info

Publication number
IL163526A0
IL163526A0 IL16352603A IL16352603A IL163526A0 IL 163526 A0 IL163526 A0 IL 163526A0 IL 16352603 A IL16352603 A IL 16352603A IL 16352603 A IL16352603 A IL 16352603A IL 163526 A0 IL163526 A0 IL 163526A0
Authority
IL
Israel
Prior art keywords
electronic circuits
circuits
electronic
Prior art date
Application number
IL16352603A
Other languages
English (en)
Original Assignee
Multigig Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0203605A external-priority patent/GB0203605D0/en
Priority claimed from GB0212869A external-priority patent/GB0212869D0/en
Priority claimed from GB0214850A external-priority patent/GB0214850D0/en
Priority claimed from GB0218834A external-priority patent/GB0218834D0/en
Priority claimed from GB0225814A external-priority patent/GB0225814D0/en
Application filed by Multigig Ltd filed Critical Multigig Ltd
Publication of IL163526A0 publication Critical patent/IL163526A0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0019—Arrangements for reducing power consumption by energy recovery or adiabatic operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Small-Scale Networks (AREA)
  • Logic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IL16352603A 2002-02-15 2003-02-14 Electronic circuits IL163526A0 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB0203605A GB0203605D0 (en) 2002-02-15 2002-02-15 Hierarchical clocking system
GB0212869A GB0212869D0 (en) 2002-06-06 2002-06-06 Timing circuit cad
GB0214850A GB0214850D0 (en) 2002-06-27 2002-06-27 Sgig
GB0218834A GB0218834D0 (en) 2002-08-14 2002-08-14 Fast synchronous interconnect improved RTWO 4 phase
GB0225814A GB0225814D0 (en) 2002-11-06 2002-11-06 High accuracy high power buffer
PCT/GB2003/000719 WO2003069452A2 (en) 2002-02-15 2003-02-14 Electronic circuits

Publications (1)

Publication Number Publication Date
IL163526A0 true IL163526A0 (en) 2005-12-18

Family

ID=27739405

Family Applications (1)

Application Number Title Priority Date Filing Date
IL16352603A IL163526A0 (en) 2002-02-15 2003-02-14 Electronic circuits

Country Status (9)

Country Link
US (1) US20050225365A1 (ko)
EP (1) EP1476801A2 (ko)
KR (1) KR20040105721A (ko)
CN (1) CN1647012A (ko)
AU (1) AU2003208422A1 (ko)
CA (1) CA2476379A1 (ko)
GB (2) GB2419437B (ko)
IL (1) IL163526A0 (ko)
WO (1) WO2003069452A2 (ko)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7209065B2 (en) * 2004-07-27 2007-04-24 Multigig, Inc. Rotary flash ADC
JP4645238B2 (ja) * 2005-03-09 2011-03-09 日本電気株式会社 半導体装置
US7571406B2 (en) * 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
US7405593B2 (en) * 2005-10-28 2008-07-29 Fujitsu Limited Systems and methods for transmitting signals across integrated circuit chips
WO2007120361A2 (en) 2005-12-27 2007-10-25 Multigig Inc. Rotary clock flash analog to digital converter system and method
US7307483B2 (en) 2006-02-03 2007-12-11 Fujitsu Limited Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability
US7546500B2 (en) * 2006-03-02 2009-06-09 Synopsys, Inc. Slack-based transition-fault testing
US7716511B2 (en) * 2006-03-08 2010-05-11 Freescale Semiconductor, Inc. Dynamic timing adjustment in a circuit device
WO2007109743A2 (en) * 2006-03-21 2007-09-27 Multigig Inc. Frequency divider
US8300798B1 (en) 2006-04-03 2012-10-30 Wai Wu Intelligent communication routing system and method
JP2008004741A (ja) * 2006-06-22 2008-01-10 Matsushita Electric Ind Co Ltd 半導体集積回路及びそれを備えた情報機器、通信機器、ａｖ機器及び移動体
US8913978B2 (en) * 2007-04-09 2014-12-16 Analog Devices, Inc. RTWO-based down converter
US7646230B2 (en) * 2007-09-21 2010-01-12 Siemens Industry, Inc. Devices, systems, and methods for reducing signals
US8132137B1 (en) * 2007-11-10 2012-03-06 Altera Corporation Prediction of dynamic current waveform and spectrum in a semiconductor device
TW201009586A (en) * 2008-08-27 2010-03-01 Macroblock Inc Coordinated operation circuit
JP5743063B2 (ja) * 2011-02-09 2015-07-01 ラピスセミコンダクタ株式会社 半導体集積回路、半導体チップ、及び半導体集積回路の設計手法
US8769343B2 (en) * 2011-06-10 2014-07-01 Nxp B.V. Compliance mode detection from limited information
US8581668B2 (en) 2011-12-20 2013-11-12 Analog Devices, Inc. Oscillator regeneration device
US8736340B2 (en) * 2012-06-27 2014-05-27 International Business Machines Corporation Differential clock signal generator
US9866174B2 (en) 2014-10-06 2018-01-09 Drexel University Resonant frequency divider design methodology for dynamic frequency scaling
US9484896B2 (en) * 2014-10-06 2016-11-01 Drexel University Resonant frequency divider design methodology for dynamic frequency scaling
US9971858B1 (en) * 2015-02-20 2018-05-15 Altera Corporation Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
US9710591B1 (en) * 2015-02-20 2017-07-18 Altera Corporation Method and apparatus for performing register retiming in the presence of timing analysis exceptions
US10860771B2 (en) * 2016-02-08 2020-12-08 Chaologix, Inc. Side channel aware automatic place and route
US10247777B1 (en) * 2016-11-10 2019-04-02 Teseda Corporation Detecting and locating shoot-through timing failures in a semiconductor integrated circuit
CN106874548B (zh) * 2017-01-10 2020-04-28 华南理工大学 一种基于双重傅里叶变换分析逆变器的方法
JP7066920B2 (ja) * 2018-09-28 2022-05-13 ラム リサーチ コーポレーション プラズマチャンバの電極への電力送出を最適化するシステムおよび方法
US10852761B2 (en) 2018-12-13 2020-12-01 Ati Technologies Ulc Computing system with automated video memory overclocking
US11264949B2 (en) 2020-06-10 2022-03-01 Analog Devices International Unlimited Company Apparatus and methods for rotary traveling wave oscillators
CN111965485B (zh) * 2020-08-04 2023-11-14 许继集团有限公司 一种用于输电线路行波测距的数据处理系统及方法
FR3129501B1 (fr) * 2021-11-23 2023-10-13 St Microelectronics Rousset Dispositif à sortie synchrone

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3538450A (en) * 1968-11-04 1970-11-03 Collins Radio Co Phase locked loop with digital capacitor and varactor tuned oscillator
US3651334A (en) * 1969-12-08 1972-03-21 American Micro Syst Two-phase ratioless logic circuit with delayless output
US4562365A (en) * 1983-01-06 1985-12-31 Commodore Business Machines Inc. Clocked self booting logical "EXCLUSIVE OR" circuit
US4599528A (en) * 1983-01-17 1986-07-08 Commodore Business Machines Inc. Self booting logical or circuit
US4570085A (en) * 1983-01-17 1986-02-11 Commodore Business Machines Inc. Self booting logical AND circuit
CA1301261C (en) * 1988-04-27 1992-05-19 Wayne D. Grover Method and apparatus for clock distribution and for distributed clock synchronization
US5386585A (en) * 1993-02-03 1995-01-31 Intel Corporation Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops
US5459414A (en) * 1993-05-28 1995-10-17 At&T Corp. Adiabatic dynamic logic
US5758139A (en) * 1993-10-21 1998-05-26 Sun Microsystems, Inc. Control chains for controlling data flow in interlocked data path circuits
EP0683448B1 (en) * 1994-05-10 2002-01-09 Intel Corporation Method and apparatus for synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio
US5627482A (en) * 1996-02-07 1997-05-06 Ceridian Corporation Electronic digital clock distribution system
JP4130006B2 (ja) * 1998-04-28 2008-08-06 富士通株式会社 半導体装置
US6163174A (en) * 1998-05-26 2000-12-19 The University Of Rochester Digital buffer circuits
US6188286B1 (en) * 1999-03-30 2001-02-13 Infineon Technologies North America Corp. Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
US6460165B1 (en) * 1999-06-17 2002-10-01 University Of Rochester Model for simulating tree structured VLSI interconnect
US6647506B1 (en) * 1999-11-30 2003-11-11 Integrated Memory Logic, Inc. Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
US7035269B2 (en) * 2000-02-02 2006-04-25 Mcgill University Method and apparatus for distributed synchronous clocking
US6718530B2 (en) * 2002-07-29 2004-04-06 Sun Microsystems, Inc. Method and apparatus for analyzing inductive effects in a circuit layout

Also Published As

Publication number Publication date
GB0420141D0 (en) 2004-10-13
GB2419437B (en) 2006-08-16
EP1476801A2 (en) 2004-11-17
GB0510489D0 (en) 2005-06-29
CN1647012A (zh) 2005-07-27
GB2403045A (en) 2004-12-22
GB2403045B (en) 2006-02-15
AU2003208422A1 (en) 2003-09-04
WO2003069452A3 (en) 2004-04-08
CA2476379A1 (en) 2003-08-21
KR20040105721A (ko) 2004-12-16
WO2003069452A2 (en) 2003-08-21
US20050225365A1 (en) 2005-10-13
GB2419437A (en) 2006-04-26

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