IL160518A0 - Relative dynamic skew compensation of parallel data lines - Google Patents

Relative dynamic skew compensation of parallel data lines

Info

Publication number
IL160518A0
IL160518A0 IL16051802A IL16051802A IL160518A0 IL 160518 A0 IL160518 A0 IL 160518A0 IL 16051802 A IL16051802 A IL 16051802A IL 16051802 A IL16051802 A IL 16051802A IL 160518 A0 IL160518 A0 IL 160518A0
Authority
IL
Israel
Prior art keywords
data lines
parallel data
skew compensation
relative dynamic
dynamic skew
Prior art date
Application number
IL16051802A
Other languages
English (en)
Original Assignee
Hansel A Collins
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hansel A Collins filed Critical Hansel A Collins
Publication of IL160518A0 publication Critical patent/IL160518A0/xx

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IL16051802A 2001-08-29 2002-08-29 Relative dynamic skew compensation of parallel data lines IL160518A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/942,377 US6907552B2 (en) 2001-08-29 2001-08-29 Relative dynamic skew compensation of parallel data lines
PCT/US2002/030298 WO2003021521A1 (en) 2001-08-29 2002-08-29 Relative dynamic skew compensation of parallel data lines

Publications (1)

Publication Number Publication Date
IL160518A0 true IL160518A0 (en) 2004-07-25

Family

ID=25478000

Family Applications (1)

Application Number Title Priority Date Filing Date
IL16051802A IL160518A0 (en) 2001-08-29 2002-08-29 Relative dynamic skew compensation of parallel data lines

Country Status (5)

Country Link
US (2) US6907552B2 (xx)
EP (1) EP1425698A4 (xx)
JP (1) JP2005502248A (xx)
IL (1) IL160518A0 (xx)
WO (1) WO2003021521A1 (xx)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3671920B2 (ja) * 2001-11-15 2005-07-13 セイコーエプソン株式会社 スキュー調整回路及びスキュー調整方法
US20030112827A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Method and apparatus for deskewing parallel serial data channels using asynchronous elastic buffers
US7170907B1 (en) * 2002-02-15 2007-01-30 Marvell Semiconductor Israel Ltd. Dynamic alignment for data on a parallel bus
US7308004B1 (en) * 2002-03-06 2007-12-11 Redback Networks, Inc. Method and apparatus of multiplexing and demultiplexing communication signals
US7130367B1 (en) * 2002-04-09 2006-10-31 Applied Micro Circuits Corporation Digital delay lock loop for setup and hold time enhancement
US7577171B2 (en) * 2002-08-06 2009-08-18 Broadcom Corporation Source centered clock supporting quad 10 GBPS serial interface
JP4467233B2 (ja) * 2002-12-24 2010-05-26 株式会社日立製作所 位相調整装置、位相調整方法および高速並列信号用スキュー補正装置
US7237216B2 (en) * 2003-02-21 2007-06-26 Infineon Technologies Ag Clock gating approach to accommodate infrequent additional processing latencies
DE102004014450A1 (de) * 2003-03-26 2005-02-10 Infineon Technologies Ag Verfahren zum Messen und Kompensieren von Versatz von Datenübertragungsleitungen
US7240249B2 (en) * 2003-06-26 2007-07-03 International Business Machines Corporation Circuit for bit skew suppression in high speed multichannel data transmission
US7295639B1 (en) * 2003-07-18 2007-11-13 Xilinx, Inc. Distributed adaptive channel bonding control for improved tolerance of inter-channel skew
JP4291225B2 (ja) * 2004-06-30 2009-07-08 富士通株式会社 パラレルデータを受信する装置および方法
WO2006020559A2 (en) * 2004-08-09 2006-02-23 Arris International, Inc. Very high speed cable modem for increasing bandwidth
US7373539B2 (en) * 2005-01-31 2008-05-13 Freescale Semiconductor, Inc. Parallel path alignment method and apparatus
US20060222126A1 (en) * 2005-03-31 2006-10-05 Stratus Technologies Bermuda Ltd. Systems and methods for maintaining synchronicity during signal transmission
US20060222125A1 (en) * 2005-03-31 2006-10-05 Edwards John W Jr Systems and methods for maintaining synchronicity during signal transmission
US7457978B2 (en) * 2005-05-09 2008-11-25 Micron Technology, Inc. Adjustable byte lane offset for memory module to reduce skew
US7437643B2 (en) * 2005-06-21 2008-10-14 Intel Corporation Automated BIST execution scheme for a link
US7448015B2 (en) * 2006-05-19 2008-11-04 International Business Machines Corporation Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
US7536579B2 (en) * 2006-08-03 2009-05-19 Avalon Microelectronics, Inc. Skew-correcting apparatus using iterative approach
US7546494B2 (en) * 2006-08-03 2009-06-09 Avalon Microelectronics Inc. Skew-correcting apparatus using dual loopback
US7760836B2 (en) * 2006-08-03 2010-07-20 Avalon Microelectronics, Inc. Skew-correcting apparatus using external communications element
US9111010B2 (en) * 2008-12-31 2015-08-18 International Business Machines Corporation Search results display for weighted multi-term searches
US8199782B2 (en) 2009-02-20 2012-06-12 Altera Canada Co. Method of multiple lane distribution (MLD) deskew
TWI410949B (zh) * 2009-10-13 2013-10-01 Himax Tech Ltd 資料驅動器與用以決定資料驅動器之最佳偏移之方法
US8582706B2 (en) * 2009-10-29 2013-11-12 National Instruments Corporation Training a data path for parallel data transfer
KR20110110904A (ko) * 2010-04-02 2011-10-10 삼성전자주식회사 송수신 시스템, 수신기 및 그것의 비대칭 보상 방법
US9985634B2 (en) 2010-05-20 2018-05-29 Kandou Labs, S.A. Data-driven voltage regulator
US9077386B1 (en) 2010-05-20 2015-07-07 Kandou Labs, S.A. Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication
US9251873B1 (en) 2010-05-20 2016-02-02 Kandou Labs, S.A. Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications
US9288082B1 (en) 2010-05-20 2016-03-15 Kandou Labs, S.A. Circuits for efficient detection of vector signaling codes for chip-to-chip communication using sums of differences
US9059850B2 (en) * 2012-03-29 2015-06-16 Broadcom Corporation Data alignment over multiple physical lanes
US11334509B2 (en) 2013-03-12 2022-05-17 Uniquify, Inc. Continuous adaptive data capture optimization for interface circuits
US8941423B2 (en) * 2013-03-12 2015-01-27 Uniquify, Incorporated Method for operating a circuit including a timing calibration function
US9544092B2 (en) * 2013-03-13 2017-01-10 Altera Corporation Apparatus for improved communication and associated methods
WO2014172377A1 (en) 2013-04-16 2014-10-23 Kandou Labs, S.A. Methods and systems for high bandwidth communications interface
CN105393512B (zh) 2013-06-25 2019-06-28 康杜实验室公司 具有低接收器复杂度的向量信令
US9806761B1 (en) 2014-01-31 2017-10-31 Kandou Labs, S.A. Methods and systems for reduction of nearest-neighbor crosstalk
US9100232B1 (en) 2014-02-02 2015-08-04 Kandou Labs, S.A. Method for code evaluation using ISI ratio
CN106105123B (zh) 2014-02-28 2019-06-28 康杜实验室公司 用于发送时钟嵌入式向量信令码的方法和系统
US9509437B2 (en) 2014-05-13 2016-11-29 Kandou Labs, S.A. Vector signaling code with improved noise margin
US9112550B1 (en) 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications
WO2016007863A2 (en) 2014-07-10 2016-01-14 Kandou Labs, S.A. Vector signaling codes with increased signal to noise characteristics
US9432082B2 (en) 2014-07-17 2016-08-30 Kandou Labs, S.A. Bus reversable orthogonal differential vector signaling codes
CN106664272B (zh) 2014-07-21 2020-03-27 康杜实验室公司 从多点通信信道接收数据的方法和装置
WO2016019384A1 (en) 2014-08-01 2016-02-04 Kandou Labs, S.A. Orthogonal differential vector signaling codes with embedded clock
US9674014B2 (en) 2014-10-22 2017-06-06 Kandou Labs, S.A. Method and apparatus for high speed chip-to-chip communications
KR102517583B1 (ko) 2015-06-26 2023-04-03 칸도우 랩스 에스에이 고속 통신 시스템
US10055372B2 (en) 2015-11-25 2018-08-21 Kandou Labs, S.A. Orthogonal differential vector signaling codes with embedded clock
CN108781060B (zh) 2016-01-25 2023-04-14 康杜实验室公司 具有增强的高频增益的电压采样驱动器
US10003454B2 (en) 2016-04-22 2018-06-19 Kandou Labs, S.A. Sampler with low input kickback
WO2017185072A1 (en) 2016-04-22 2017-10-26 Kandou Labs, S.A. High performance phase locked loop
WO2017185070A1 (en) 2016-04-22 2017-10-26 Kandou Labs, S.A. Calibration apparatus and method for sampler with adjustable high frequency gain
EP3449606A4 (en) 2016-04-28 2019-11-27 Kandou Labs S.A. LOW POWER MULTILAYER ATTACK CIRCUIT
US10193716B2 (en) 2016-04-28 2019-01-29 Kandou Labs, S.A. Clock data recovery with decision feedback equalization
EP3449379B1 (en) 2016-04-28 2021-10-06 Kandou Labs S.A. Vector signaling codes for densely-routed wire groups
US10153591B2 (en) 2016-04-28 2018-12-11 Kandou Labs, S.A. Skew-resistant multi-wire channel
US10749756B2 (en) * 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane
US9906358B1 (en) 2016-08-31 2018-02-27 Kandou Labs, S.A. Lock detector for phase lock loop
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops
US10200188B2 (en) 2016-10-21 2019-02-05 Kandou Labs, S.A. Quadrature and duty cycle error correction in matrix phase lock loop
US10200218B2 (en) 2016-10-24 2019-02-05 Kandou Labs, S.A. Multi-stage sampler with increased gain
US10372665B2 (en) 2016-10-24 2019-08-06 Kandou Labs, S.A. Multiphase data receiver with distributed DFE
CN110612500B (zh) 2017-02-28 2023-08-04 康杜实验室公司 多线路时偏的测量和校正方法
US10116468B1 (en) 2017-06-28 2018-10-30 Kandou Labs, S.A. Low power chip-to-chip bidirectional communications
US10686583B2 (en) * 2017-07-04 2020-06-16 Kandou Labs, S.A. Method for measuring and correcting multi-wire skew
US10203226B1 (en) 2017-08-11 2019-02-12 Kandou Labs, S.A. Phase interpolation circuit
KR102371823B1 (ko) * 2017-12-04 2022-03-07 주식회사 엘엑스세미콘 디스플레이 장치에서의 데이터송수신방법 및 디스플레이 패널구동장치
US10326623B1 (en) 2017-12-08 2019-06-18 Kandou Labs, S.A. Methods and systems for providing multi-stage distributed decision feedback equalization
US10554380B2 (en) 2018-01-26 2020-02-04 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
US10243614B1 (en) 2018-01-26 2019-03-26 Kandou Labs, S.A. Method and system for calibrating multi-wire skew
CN110224786B (zh) * 2018-03-01 2022-05-13 京东方科技集团股份有限公司 数据传输方法、装置、系统及显示装置
KR102541227B1 (ko) 2018-06-11 2023-06-08 칸도우 랩스 에스에이 직교 차동 벡터 시그널링 코드들에 대한 스큐 검출 및 보정
US11687471B2 (en) * 2020-03-27 2023-06-27 Sk Hynix Nand Product Solutions Corp. Solid state drive with external software execution to effect internal solid-state drive operations
CN118072693B (zh) * 2024-04-12 2024-07-30 北京数字光芯集成电路设计有限公司 一种基于相位的mipi偏斜纠正方法和系统
CN118713809A (zh) * 2024-08-27 2024-09-27 山东云海国创云计算装备产业创新中心有限公司 一种并行总线数据传输系统、方法及存储介质

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408473A (en) * 1992-03-03 1995-04-18 Digital Equipment Corporation Method and apparatus for transmission of communication signals over two parallel channels
JP2694807B2 (ja) * 1993-12-16 1997-12-24 日本電気株式会社 データ伝送方式
US5513377A (en) * 1994-06-17 1996-04-30 International Business Machines Corporation Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
US5719862A (en) * 1996-05-14 1998-02-17 Pericom Semiconductor Corp. Packet-based dynamic de-skewing for network switch with local or central clock
US6031847A (en) * 1997-07-01 2000-02-29 Silicon Graphics, Inc Method and system for deskewing parallel bus channels
TW419924B (en) * 1998-02-16 2001-01-21 Nippon Telegraph & Telephone Channel-to-channel skew compensation
US6636993B1 (en) * 1999-02-12 2003-10-21 Fujitsu Limited System and method for automatic deskew across a high speed, parallel interconnection
US6920576B2 (en) * 2001-05-31 2005-07-19 Koninklijke Philips Electronics N.V. Parallel data communication having multiple sync codes

Also Published As

Publication number Publication date
US20030046618A1 (en) 2003-03-06
US6907552B2 (en) 2005-06-14
JP2005502248A (ja) 2005-01-20
EP1425698A4 (en) 2007-05-16
EP1425698A1 (en) 2004-06-09
WO2003021521A1 (en) 2003-03-13
US20050229049A1 (en) 2005-10-13

Similar Documents

Publication Publication Date Title
IL160518A0 (en) Relative dynamic skew compensation of parallel data lines
HUP0202713A3 (en) Pteridinones as kinase inhibitors
AU2002310456A1 (en) Compensation data prediction
EP1461703A4 (en) DYNAMIC COPIER PROTECTION FOR OPTICAL MEDIA
AU2002305641A8 (en) Dynamic change of address notification
AU2002228316A1 (en) Carbazole derivatives and their uses as heparanase inhibitors
GB2379602B (en) Corner computer workcenter
IL150002A0 (en) Computer arrangement using non-refreshed dram
AU2002237657A1 (en) Indole-type inhibitors of p38 kinase
GB2379845B (en) Process for the transfer of data
GB0101412D0 (en) Computer graphics
AU2001266784A1 (en) Authentication of electronic data
GB0113051D0 (en) Compensation of workflow applications
AU2002341818A1 (en) Relative dynamic skew compensation of parallel data lines
EP1419579A4 (en) COMPENSATING FOR DIFFERENCES BETWEEN CLOCK SIGNALS
AU2003264781A8 (en) Dynamic access to data
GB0200595D0 (en) Quantitation of differential expression
GB0109278D0 (en) Enzyme inhibitors
GB0130786D0 (en) Writing desk
EP1430302A4 (en) Glycosaminoglycan INHIBITORS
TW512697U (en) Improved structure of computer desk
TW499897U (en) Improved structure of computer desk
TW488226U (en) Improved structure of computer desk
TW507558U (en) Structure of desk for laptop computer
TW452321U (en) Improvement of outer connecting box for computer