IL128178A0 - Digital adder circuit - Google Patents

Digital adder circuit

Info

Publication number
IL128178A0
IL128178A0 IL12817897A IL12817897A IL128178A0 IL 128178 A0 IL128178 A0 IL 128178A0 IL 12817897 A IL12817897 A IL 12817897A IL 12817897 A IL12817897 A IL 12817897A IL 128178 A0 IL128178 A0 IL 128178A0
Authority
IL
Israel
Prior art keywords
adder circuit
digital adder
digital
circuit
adder
Prior art date
Application number
IL12817897A
Other languages
English (en)
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IL128178A0 publication Critical patent/IL128178A0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
IL12817897A 1996-10-02 1997-07-04 Digital adder circuit IL128178A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9620526A GB2317971B (en) 1996-10-02 1996-10-02 Digital adder circuit
PCT/GB1997/001812 WO1998014864A1 (en) 1996-10-02 1997-07-04 Digital adder circuit

Publications (1)

Publication Number Publication Date
IL128178A0 true IL128178A0 (en) 1999-11-30

Family

ID=10800811

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12817897A IL128178A0 (en) 1996-10-02 1997-07-04 Digital adder circuit

Country Status (10)

Country Link
US (1) US5951630A (de)
EP (1) EP1008033B1 (de)
JP (1) JP2001501341A (de)
KR (1) KR20000048818A (de)
CN (1) CN1232561A (de)
DE (1) DE69708160D1 (de)
GB (1) GB2317971B (de)
IL (1) IL128178A0 (de)
TW (1) TW313652B (de)
WO (1) WO1998014864A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231414B1 (en) * 2000-02-09 2007-06-12 Hewlett-Packard Development Company, L.P. Apparatus and method for performing addition of PKG recoded numbers
KR20000054275A (ko) * 2000-05-30 2000-09-05 장주욱 입력에 따라 능동적으로 재구성 가능한 고속 병렬 덧셈기
US6954773B2 (en) * 2001-09-28 2005-10-11 Intel Corporation Providing an adder with a conversion circuit in a slack propagation path
US7921148B2 (en) * 2006-08-09 2011-04-05 Infineon Technologies Ag Standard cell for arithmetic logic unit and chip card controller
CN101201731B (zh) * 2008-02-15 2010-08-18 刘杰 二进制数字减法器
US8521801B2 (en) * 2008-04-28 2013-08-27 Altera Corporation Configurable hybrid adder circuitry
US9785405B2 (en) * 2015-05-29 2017-10-10 Huawei Technologies Co., Ltd. Increment/decrement apparatus and method
CN105045556B (zh) * 2015-07-09 2018-01-23 合肥工业大学 一种动静态混合式加法器
CN113642280B (zh) * 2020-04-27 2024-06-14 中国科学院上海微系统与信息技术研究所 超导集成电路的布局方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099248A (en) * 1977-01-28 1978-07-04 Sperry Rand Corporation One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits
JPH0391832A (ja) * 1989-09-05 1991-04-17 Sony Corp 加算回路
JP2530070B2 (ja) * 1991-09-11 1996-09-04 株式会社東芝 加算器
US5499203A (en) * 1992-09-27 1996-03-12 Grundland; Nathan Logic elements for interlaced carry/borrow systems having a uniform layout
US5278783A (en) * 1992-10-30 1994-01-11 Digital Equipment Corporation Fast area-efficient multi-bit binary adder with low fan-out signals
TW253951B (de) * 1993-05-03 1995-08-11 Motorola Inc
US5465224A (en) * 1993-11-30 1995-11-07 Texas Instruments Incorporated Three input arithmetic logic unit forming the sum of a first Boolean combination of first, second and third inputs plus a second Boolean combination of first, second and third inputs
US5596763A (en) * 1993-11-30 1997-01-21 Texas Instruments Incorporated Three input arithmetic logic unit forming mixed arithmetic and boolean combinations
US5493524A (en) * 1993-11-30 1996-02-20 Texas Instruments Incorporated Three input arithmetic logic unit employing carry propagate logic
US5485411A (en) * 1993-11-30 1996-01-16 Texas Instruments Incorporated Three input arithmetic logic unit forming the sum of a first input anded with a first boolean combination of a second input and a third input plus a second boolean combination of the second and third inputs

Also Published As

Publication number Publication date
GB2317971A (en) 1998-04-08
WO1998014864A1 (en) 1998-04-09
JP2001501341A (ja) 2001-01-30
KR20000048818A (ko) 2000-07-25
TW313652B (en) 1997-08-21
EP1008033A1 (de) 2000-06-14
GB2317971B (en) 2000-12-06
CN1232561A (zh) 1999-10-20
EP1008033B1 (de) 2001-11-07
GB9620526D0 (en) 1996-11-20
DE69708160D1 (de) 2001-12-13
US5951630A (en) 1999-09-14

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