IL120748A - Method and apparatus of reducing the number of clock cycles required for communication of information packets - Google Patents

Method and apparatus of reducing the number of clock cycles required for communication of information packets

Info

Publication number
IL120748A
IL120748A IL12074896A IL12074896A IL120748A IL 120748 A IL120748 A IL 120748A IL 12074896 A IL12074896 A IL 12074896A IL 12074896 A IL12074896 A IL 12074896A IL 120748 A IL120748 A IL 120748A
Authority
IL
Israel
Prior art keywords
reducing
communication
clock cycles
information packets
cycles required
Prior art date
Application number
IL12074896A
Other languages
English (en)
Other versions
IL120748A0 (en
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IL120748A0 publication Critical patent/IL120748A0/xx
Publication of IL120748A publication Critical patent/IL120748A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IL12074896A 1996-03-01 1996-06-27 Method and apparatus of reducing the number of clock cycles required for communication of information packets IL120748A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/609,175 US5815673A (en) 1996-03-01 1996-03-01 Method and apparatus for reducing latency time on an interface by overlapping transmitted packets
PCT/US1996/010853 WO1997032333A1 (fr) 1996-03-01 1996-06-27 Procede et dispositif de reduction du temps de latence sur une interface, par chevauchement des paquets transmis

Publications (2)

Publication Number Publication Date
IL120748A0 IL120748A0 (en) 1998-02-22
IL120748A true IL120748A (en) 1999-11-30

Family

ID=24439651

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12074896A IL120748A (en) 1996-03-01 1996-06-27 Method and apparatus of reducing the number of clock cycles required for communication of information packets

Country Status (11)

Country Link
US (1) US5815673A (fr)
EP (1) EP0829095B1 (fr)
JP (1) JPH11504741A (fr)
KR (1) KR100266963B1 (fr)
CN (1) CN1107956C (fr)
AU (1) AU6390296A (fr)
DE (1) DE69625685T2 (fr)
IL (1) IL120748A (fr)
RU (1) RU2189698C2 (fr)
TW (1) TW299409B (fr)
WO (2) WO1997032308A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091707A (en) * 1997-12-18 2000-07-18 Advanced Micro Devices, Inc. Methods and apparatus for preventing under-flow conditions in a multiple-port switching device
GB9809203D0 (en) * 1998-04-29 1998-07-01 Sgs Thomson Microelectronics Packet distribution in a microcomputer
US6134701A (en) * 1998-09-22 2000-10-17 Via Technologies, Inc. Computer motherboard with a control chip having specific pin arrangement for fast cache access
CN100370841C (zh) * 2004-11-19 2008-02-20 华为技术有限公司 一种通信接口间消息的传输方法
EP2320327A1 (fr) * 2009-11-09 2011-05-11 Imec Dispositif de transfert de données

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418409A (en) * 1980-03-07 1983-11-29 Ibm Corporation Byte data activity compression
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4914653A (en) * 1986-12-22 1990-04-03 American Telephone And Telegraph Company Inter-processor communication protocol
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US4937791A (en) * 1988-06-02 1990-06-26 The California Institute Of Technology High performance dynamic ram interface
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5598581A (en) * 1993-08-06 1997-01-28 Cisco Sytems, Inc. Variable latency cut through bridge for forwarding packets in response to user's manual adjustment of variable latency threshold point while the bridge is operating
US5548797A (en) * 1994-10-03 1996-08-20 International Business Machines Corporation Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal
US5623638A (en) * 1994-11-22 1997-04-22 Advanced Micro Devices, Inc. Memory control unit with programmable edge generator to minimize delay periods for critical DRAM timing parameters
US5649175A (en) * 1995-08-10 1997-07-15 Cirrus Logic, Inc. Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement

Also Published As

Publication number Publication date
KR100266963B1 (ko) 2000-10-02
EP0829095A1 (fr) 1998-03-18
EP0829095B1 (fr) 2003-01-08
TW299409B (en) 1997-03-01
EP0829095A4 (fr) 2000-04-05
IL120748A0 (en) 1998-02-22
RU2189698C2 (ru) 2002-09-20
CN1107956C (zh) 2003-05-07
WO1997032308A1 (fr) 1997-09-04
WO1997032333A1 (fr) 1997-09-04
CN1183164A (zh) 1998-05-27
DE69625685D1 (de) 2003-02-13
JPH11504741A (ja) 1999-04-27
AU6390296A (en) 1997-09-16
DE69625685T2 (de) 2003-10-23
KR19990008189A (ko) 1999-01-25
US5815673A (en) 1998-09-29

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Legal Events

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