IE52351B1 - A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device - Google Patents

A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device

Info

Publication number
IE52351B1
IE52351B1 IE631/81A IE63181A IE52351B1 IE 52351 B1 IE52351 B1 IE 52351B1 IE 631/81 A IE631/81 A IE 631/81A IE 63181 A IE63181 A IE 63181A IE 52351 B1 IE52351 B1 IE 52351B1
Authority
IE
Ireland
Prior art keywords
semiconductor
groove
region
layer
polycrystal
Prior art date
Application number
IE631/81A
Other languages
English (en)
Other versions
IE810631L (en
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of IE810631L publication Critical patent/IE810631L/xx
Publication of IE52351B1 publication Critical patent/IE52351B1/en

Links

Classifications

    • H10P34/42—
    • H10W10/00—
    • H10W10/01—
    • H10W10/041—
    • H10W10/40—
    • H10W20/065—
    • H10W20/49—

Landscapes

  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
IE631/81A 1980-03-25 1981-03-20 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device IE52351B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3807080A JPS56146247A (en) 1980-03-25 1980-03-25 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
IE810631L IE810631L (en) 1981-09-25
IE52351B1 true IE52351B1 (en) 1987-09-30

Family

ID=12515223

Family Applications (1)

Application Number Title Priority Date Filing Date
IE631/81A IE52351B1 (en) 1980-03-25 1981-03-20 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device

Country Status (5)

Country Link
US (1) US4497665A (enExample)
EP (1) EP0036764B1 (enExample)
JP (1) JPS56146247A (enExample)
DE (1) DE3175640D1 (enExample)
IE (1) IE52351B1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105551A (ja) * 1981-11-20 1983-06-23 Fujitsu Ltd 半導体装置
JPS59155944A (ja) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp 半導体装置の製造方法
US4610730A (en) * 1984-12-20 1986-09-09 Trw Inc. Fabrication process for bipolar devices
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
JPS6467945A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Wiring layer formed on buried dielectric and manufacture thereof
CN1034228C (zh) * 1993-08-04 1997-03-12 株洲冶炼厂 一种自萃除有色金属的富铁有机相中除铁的方法
DE19538005A1 (de) * 1995-10-12 1997-04-17 Fraunhofer Ges Forschung Verfahren zum Erzeugen einer Grabenisolation in einem Substrat
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956033A (en) * 1974-01-03 1976-05-11 Motorola, Inc. Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector
US4037306A (en) * 1975-10-02 1977-07-26 Motorola, Inc. Integrated circuit and method
US4048649A (en) * 1976-02-06 1977-09-13 Transitron Electronic Corporation Superintegrated v-groove isolated bipolar and vmos transistors
DE2837800A1 (de) * 1978-08-30 1980-03-13 Philips Patentverwaltung Verfahren zum herstellen von halbleiterbauelementen
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4214918A (en) * 1978-10-12 1980-07-29 Stanford University Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS6043024B2 (ja) * 1978-12-30 1985-09-26 富士通株式会社 半導体装置の製造方法
DE3072028D1 (en) * 1979-11-23 1987-10-15 Alcatel Nv Dielectrically insulated semiconductor component and process for its manufacture
US4295924A (en) * 1979-12-17 1981-10-20 International Business Machines Corporation Method for providing self-aligned conductor in a V-groove device
US4260436A (en) * 1980-02-19 1981-04-07 Harris Corporation Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching

Also Published As

Publication number Publication date
EP0036764A3 (en) 1984-01-18
DE3175640D1 (en) 1987-01-08
IE810631L (en) 1981-09-25
JPS6227744B2 (enExample) 1987-06-16
EP0036764B1 (en) 1986-11-20
EP0036764A2 (en) 1981-09-30
US4497665A (en) 1985-02-05
JPS56146247A (en) 1981-11-13

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