IE41962L - Pcm t.d.m. data transmission system - Google Patents
Pcm t.d.m. data transmission systemInfo
- Publication number
- IE41962L IE41962L IE752659A IE265975A IE41962L IE 41962 L IE41962 L IE 41962L IE 752659 A IE752659 A IE 752659A IE 265975 A IE265975 A IE 265975A IE 41962 L IE41962 L IE 41962L
- Authority
- IE
- Ireland
- Prior art keywords
- signal
- shift register
- scrambler
- message
- monitor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/40—Monitoring; Testing of relay systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Dc Digital Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
1528900 t.d.m. data transmission SIEMENS AG 28 Nov 1975 [19 Dec 1974] 48928/75 Heading H4M In a t.d.m. system wherein a transmission path extends between end stations (not shown) via intermediate stations each containing a receiving portion Fig. 2, and a transmitting portion Fig. 1, the data being in the form of frames with frame and/or message control words acting as a monitoring signal, see Specification 1,398,961, data for transmission passing serially into shift register SRI, logic unit SL ensuring that the monitoring signal bits are interleaved, using the parallel shift register inputs into the message, there is provided a scrambler Scl {comprising a shift register with feedback from a plurality of bit positions to its input), whose pseudo-random output is combined at exclusive OR gate EXOR1 {modulo-2 adder} with the multiplex signal from the register SR1, the scrambler being reset at a given bit position {start of the message control word} of the frame, a corresponding scrambler Sc2, correspondingly reset, and exclusive or EXOR2 at the subsequent receiving portion reconstituting the multiplex signal for passage to shift register SR2 in which the message and monitor signal are separated. Should the shift register SRI cease to provide an output, the output of Sc1 is transmitted to provide a standby signal pattern. Under normal conditions of reception, logic unit EL compares the separated monitor signal with a locally generated one, the result SYN passing to a synch monitor. Should realignment be necessary, scrambler Sc2 is stopped, unit EL receiving the scrambled monitor signal for comparison with a corresponding locally generated signal. Scrambling of the transmitted signal avoids bunching in its spectral density. The scramblers may each have as many shift register stages as there are bit positions in the frame control word.
[GB1528900A]
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742460234 DE2460234B2 (en) | 1974-12-19 | 1974-12-19 | REPLACEMENT PULSE GENERATOR |
Publications (2)
Publication Number | Publication Date |
---|---|
IE41962L true IE41962L (en) | 1976-06-19 |
IE41962B1 IE41962B1 (en) | 1980-05-07 |
Family
ID=5933904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IE2659/75A IE41962B1 (en) | 1974-12-19 | 1975-12-05 | Improvements in or relating to data transmission systems |
Country Status (8)
Country | Link |
---|---|
JP (2) | JPS5188118A (en) |
BE (1) | BE836880R (en) |
DE (1) | DE2460234B2 (en) |
DK (1) | DK145838C (en) |
GB (1) | GB1528900A (en) |
IE (1) | IE41962B1 (en) |
IT (1) | IT1054678B (en) |
LU (1) | LU73830A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0018453A1 (en) * | 1979-05-02 | 1980-11-12 | THE PLESSEY COMPANY plc | Synthesis arrangements for use in digital data transmission systems |
JPS61169048A (en) * | 1985-01-21 | 1986-07-30 | Nippon Telegr & Teleph Corp <Ntt> | Digital repeater |
CA1251583A (en) * | 1985-03-28 | 1989-03-21 | Yoshiaki Yato | Multiplex system |
JPS61255142A (en) * | 1985-05-08 | 1986-11-12 | Nec Corp | Bit addition device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4843209A (en) * | 1971-10-01 | 1973-06-22 | ||
JPS5532060B2 (en) * | 1973-01-17 | 1980-08-22 |
-
1974
- 1974-12-19 DE DE19742460234 patent/DE2460234B2/en active Granted
-
1975
- 1975-11-19 LU LU73830A patent/LU73830A1/xx unknown
- 1975-11-28 GB GB48928/75A patent/GB1528900A/en not_active Expired
- 1975-12-05 IE IE2659/75A patent/IE41962B1/en unknown
- 1975-12-16 IT IT30325/75A patent/IT1054678B/en active
- 1975-12-18 DK DK577175A patent/DK145838C/en not_active IP Right Cessation
- 1975-12-19 JP JP50151701A patent/JPS5188118A/ja active Pending
- 1975-12-19 BE BE162947A patent/BE836880R/en not_active IP Right Cessation
-
1982
- 1982-08-18 JP JP1982124120U patent/JPS5859250U/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DK577175A (en) | 1976-06-20 |
DE2460234A1 (en) | 1976-06-24 |
DE2460234B2 (en) | 1976-12-02 |
BE836880R (en) | 1976-04-16 |
IE41962B1 (en) | 1980-05-07 |
IT1054678B (en) | 1981-11-30 |
JPS5859250U (en) | 1983-04-21 |
LU73830A1 (en) | 1976-06-11 |
JPS5188118A (en) | 1976-08-02 |
DK145838B (en) | 1983-03-14 |
DK145838C (en) | 1983-09-05 |
GB1528900A (en) | 1978-10-18 |
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