IE41962B1 - Improvements in or relating to data transmission systems - Google Patents

Improvements in or relating to data transmission systems

Info

Publication number
IE41962B1
IE41962B1 IE2659/75A IE265975A IE41962B1 IE 41962 B1 IE41962 B1 IE 41962B1 IE 2659/75 A IE2659/75 A IE 2659/75A IE 265975 A IE265975 A IE 265975A IE 41962 B1 IE41962 B1 IE 41962B1
Authority
IE
Ireland
Prior art keywords
scrambler
signal
shift register
transmission
monitoring signal
Prior art date
Application number
IE2659/75A
Other versions
IE41962L (en
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IE41962L publication Critical patent/IE41962L/en
Publication of IE41962B1 publication Critical patent/IE41962B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/14Monitoring arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/40Monitoring; Testing of relay systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/12Arrangements providing for calling or supervisory signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

1528900 t.d.m. data transmission SIEMENS AG 28 Nov 1975 [19 Dec 1974] 48928/75 Heading H4M In a t.d.m. system wherein a transmission path extends between end stations (not shown) via intermediate stations each containing a receiving portion Fig. 2, and a transmitting portion Fig. 1, the data being in the form of frames with frame and/or message control words acting as a monitoring signal, see Specification 1,398,961, data for transmission passing serially into shift register SRI, logic unit SL ensuring that the monitoring signal bits are interleaved, using the parallel shift register inputs into the message, there is provided a scrambler Scl {comprising a shift register with feedback from a plurality of bit positions to its input), whose pseudo-random output is combined at exclusive OR gate EXOR1 {modulo-2 adder} with the multiplex signal from the register SR1, the scrambler being reset at a given bit position {start of the message control word} of the frame, a corresponding scrambler Sc2, correspondingly reset, and exclusive or EXOR2 at the subsequent receiving portion reconstituting the multiplex signal for passage to shift register SR2 in which the message and monitor signal are separated. Should the shift register SRI cease to provide an output, the output of Sc1 is transmitted to provide a standby signal pattern. Under normal conditions of reception, logic unit EL compares the separated monitor signal with a locally generated one, the result SYN passing to a synch monitor. Should realignment be necessary, scrambler Sc2 is stopped, unit EL receiving the scrambled monitor signal for comparison with a corresponding locally generated signal. Scrambling of the transmitted signal avoids bunching in its spectral density. The scramblers may each have as many shift register stages as there are bit positions in the frame control word.

Description

This invention relates bo a fc.d.rii. dabs transmission system including a transmission path extending between two end stations which transmission path is divided by intermediate stations into a plurality of transmission sections.
Such a transmission system contains one transmission path in each transmission direction, a multiplex device being arranged at the beginning of the relevant transmission path and serving to divide up the individual trans1° mission channels amongst time slots in the transmission signal. At the end of the relevant transmission path is arranged a corresponding demultiplex device which serves t.o distribute the incoming signal bits amongst the associated receiving channels.
The intermediate stations are constituted by line terminal devices, and each transmission section generally contains a plurality of intermediate regenerators.
For monitoring purposes it is known for each line terminal device to emit periodically a monitoring signal together with the signal sequence which is to be transmitted, thus producing a transmission signal which possesses a periodic frame structure. The monitoring signal usually comprises a frame synchronising code word in a predetermined position in alternate frames and a message word in Lhe corresponding position in the other frames (see British Patent Specification No. l,39%96l).
At the end of each transmission section the monitoring signal is gated out of the received signal sequence and is compared with a theoretical value. There are three possible results to this comparison, namely to the effect that the preceding transmission section is entirely free of disturbance, of that the preceding transmission section is slightly disturbed, in which case the signal transmission is not yet impaired to any substantial extent, or that the preceding transmission section is so heavily disturbed that no serviceable signal transmission is possihLe.
In the third case, i.e, when no bit sequence arrives from the preceding transmission section, in the intermediate station which has established this fact a standby pulse generator is activated which emits a substitute signal to the 'following transmission portion. This substitute signal serves ιo maintain synchronisation in the following transmission sections so that on the discontinuation of the disturbance in the disturbed transmission section these are immediately ready for signal transmission.
According to this invention there is provided a PCM t.d.m. data transmission system including a transmission path extending between two end stations which transmission path is divided by intermediate stations into a plurality of transmission sections, each said station being arranged to relay a sequence of individual t.d.m. signals having a periodic frame arrangement and being transmitted via said l.ransmi ssi on path, a scrambler in «•ach of said intermediate stations being arranged such that when no signal sequence is received by that intermediate station from one of the adjacent transmission se.ctiorts, a pseudo-random sequence continuously produced by the scramHer is used to provide a signal transmitted via the adjacent transmission section to which said one transmission section is to be connected by the intermediate station.
Preferably in each intermediate station the transmitting end includes an EXCLUSTVE-OR-gate connected as a modulo-2- adder one input of which is constantly fed with the pseudo-random sequence from the scrambler and another input of which is fed with the bit sequence which is to be transmitted, and the receiving end includes an identical scrambler for descrambling and which is arranged to be disconnected during realignment. Thus in the event of failure of the bit sequence which is to be transmitted, the reset scrambler is effective automatically, i.e. without an additional switch-over, to operate as the standby pulse generator.
The modulo-2-addition between the bit sequence which is to be transmitted and the scrambled text also produces a determinate scrambling of the bit sequence which is to be transmitted. This determinate scrambling of the bit sequence which is to be transmitted can be most advantageous for the transmission, as it is thus possible to' eliminate highly disturbing spectral lines at specific transmission frequencies in a simple fashion This development of the invention arises from the recognition that a modulo-2 addition with a specific addend can be cancelled hy a further modulo-2 addition with the same addend. it< an embodiment of Lhe invention which is particularly favourable with regard to the disturbing spectral lines, the scrambler consists of a shift register, which is set at a predetermined point of each frame in the timing of the frame period and whose number of stages corresponds to the number of bits in the frame code word (which is the same as for the message word) and the descrambler is of identical construction and is in each case set at the same point of the frame as the scrambler.
Advantageously the scrambler comprises an eight-stage shift, register with feedback to the input following, i.e. from the outputs of, the first, third, fifth and eighth stages.
Preferably the scrambler is arranged to scramble the monitoring signal, i.e, the frame code word and/or the message word, and for monitoring the scrambler each intermediate station includes at the receiving end a circuit arrangement which compares the received descrambled mon25 itoring signal with a signal sequence produced in said receiving end, and during realignment compares the received, scrambled monitoring signal with a predetermined signal sequence produced in said receiving end and to which should correspond said scrambled monitoring signal.
Such a monitoring arrangement is of very simple construction and requires only a low outlaj' as it is basically limited to the additional provision of a comparator at the receiving end.
Th<; invention wil‘1 be further understood from the following description by way of exalnple of an embodiment thereof with reference to the accompanying drawing, in which Figures 1 and 2 respeci.ivety schematicaIly illustrate the transmitting end and the receiving end of an intermediate station provided in a data transmission system known as the PCM 3θ system, in which the frame code word and the message word are used as monitoring signals. in each intermediate station the components of the transmitting end of the intermediate station are connected to the components of the receiving end of the intermediate station from where they receive the PCM signal sequence which is to be transmitted via the following transmission section, the pulse train signal, and further items of control information.
As shown in Fig. 1, the transmitting end of the intermediate station comprises a scrambler Scl, a pulse train central control unit TZl, an eight stage shift register SRI, a transmitting logic unit SL, an AND gate AND1, and an EXCLUSIVE-OR gate EX0R1, Via a terminal PCM1, the PCM signal sequence which is to be transmitted passes to a serial input of the eight stage shift register SRI. Individual parallel-entry inputs of the stages of the shift register SRI are connected to corresponding outputs of the transmissing logic unit SL, which, under the control of the frame code word and themessage code word pulse train from the pulse train central control unit TZl, feeds the parallel-entry inputs of the indi30 vidual stages of the shift register at specific times with the frame code word and the message word and thus interposes the latter into the PCM signals passing through the shift register. Via a terminal Pl, the - 7 41962 I ransini l.t. i ng logic unit SI. pcccivi's from t.he receiving end of l.hc intermediate station further items of control information which have been obtained by gating of the received frame code word and message word from the received PCM signal sequence. The pulse train central control unit TZ1 receives a bit pulse train derived at the receiving end of the intermediate station via a terminal Tl, and receives further items of information regarding the word and frame pulse trains via a terminal Si.
The individual pulse trains obtained in the pulse (.rain central control unit TZ1 are conducted to the shift register SRI, the transmitting logic unit SI, and the scrambler Sci which constantly emits scrambled text provide a pseudo-random sequence of bits. The scrambler Sci also receives the bit pulse train obtained at the receiving end direct from the terminal Tl. In the present case the scrambler Sci is in the form of an eightstage shift register with feedback from the outputs of the first, third, fifth and eighth stages. The output of the scrambler Sci is connected to one input of the gate AND1 which during operation is controlled via its second input from a connection 01 in such manner that it is transmissive for the output signals of the scrambler. The output PCM2 of the transmitting end of the intermediate station is formed by the output of the gate EXORI, whose inputs arc connected respectively to the output of the gate AND1 and to a serial output of the shift register SRI, The gate EXORI is connected as a modulo-2 adder so that it adds together the scrambled text, emitted by the scrambler Sci via the gate AND1 and the PCM signals emitted from the shift register SRI, including the monitoring signal which in the present case is formed from the frame code word and the message cede word.
Ii due to a fault, the PCM signals normally emitted from the shift register SRI fail to appear, then the scrambler Sci is automatically effective to function as a standby pulse generator, and the scrambling signal which it emits is fed via the gates AUDI and EXORl to the following l.ransni i ss ion section. 1.1 Lhe PCM signals fail to appear al. the input PCM1, (lie shift register SRi emits only the newly inserted monitoring signal. The pulse frame at the output, of the gate EXORl then contains only the scrambled text and the scrambled monitoring signal.
The scrambler Sci is controlled and monitored in such manner that at the beginning of the frame word (and/ or the message word in modified embodiments) it is ready to emit the scrambled text 11110000. To enable optimum monitoring of the scrambler Sci, the latter is supplied with setting pulses at such a time that at the beginning of the monitoring signal all the stages of the scrambler are prepared and functioning for supplying the text. ((110000. Accordingly to provide plenty of time for this state to be reached and checked i-ho scrambler i.s sc·!, at. tile end of the monitoring signal. The modulo-2 addition effected by the gate EXORl converts the frame code word. X001X011 into a sequence Xl10X011 and feeds it to the following transmission section.
As shown in Fig. 2 the receiving end of the intermediate station is of similar construction to the transmitting end shown in Fig. 1, the receiving end comprising a scrambler Sc2, identical to the scrambler Sci, a pulse train central control unit TZ2, an eight stage shift register SR2, a receiving logic unit EL, an AND gate AND2, and an EXCLUSIVE-OR gate EX0R2. The scrambled PCM signals including Lhe Scrambled frame code word and/ or message word are received via a terminal PCM2 and pass to a first input of the gate EX0R2. Timing signals incoming via a terminal T2 are conducted directly to the pulse train central control unit TZ2, the scrambler Sc2, and the shift register SR2. The pulse train central control unit TZ2 produces a new frame code word and a new message word pulse train and passes the latter to the shift register SR2, the receiving logic unit EL, and the scrambler Sc2.
The scrambler Sc2 is likewise controlled in such manner that in each case at the beginning of the frame word (and/or message word) it emits the scrambled text 11110000, in this case to one input of the gate AND2. During operation this gate AND2 is transmissive and feeds the scrambled text to a second input of the gate EX0R2.
The gate EX0R2 is likewise connected as a modulo-2 adder and adds the scrambled text from the scrambler Sc2 to the signals received via the terminal PCM2, for example to the scrambled frame code word which as described above has been transmitted in the form XI10X011. The original frame code word X001X011 is produced as a result of this modulo-2 addition. The original message word can also be restored in a corresponding manner.
Following this descrambling, the incoming PCM signal sequence, with frame code word and message word, is conducted to a serial input of the shift register SR2. This shift register SR2 has parallel outputs from its eight stages which are individually connected to inputs Of the receiving logic unit EL. The receiving logic unit - 10 41962 EL serves Lo gate out from the PCM signals passing through the shift register SR2 the frame code word and/or the message word, to compare the latter with a frame code word or message word produced in the receiving end of Lhe intermediate station, and the resuLL SYN of the comparison is conducted to a synchronism Monitoring unit (not shown) and thus (.he scramblers ficl and Sc2 and tlie gates ANDl, AND2, EXORl, and EX0R2 are monitored. The groups of signals passing tiirngh the shift register SR2 are conducted via a terminal PCM3 to the following transmitting end of the intermediate station for further transmission, Or to other receiving devices such as e.g. a demultiplexer. The monitoring device provided in the relevant intermediate IS station is connected via a terminal (not shown) to the scrambler Sc2 and. via a terminal (not shown) to the pulse train central control unit TZ2, so 'that the station is able to monitor itself. The pulse train central control unit TZ2 also supplies the items of information regard20 ing the frame code word and message word pulse trains via a further terminal T3 to the transmitting end of the intermediate station. During realignment, the scrambler Sc2 is disconnected and the receiving logic unit EL is switched over to compare the scrambled monitoring signal with a scrambled signal produced at the receiving end until the monitoring signal is recognised. Γη order to check intermediate regenerators arranged between the individual intermediate stations, it is possible to block the two gates ANDl and AND2 via the con30 nection 01 and a connection 02 thereby to prevent the scrambled text from being transmitted from the scramblers to the EXCLUSIVE-OR gates. Consequently there is. no 419 6 2 modulo-2 addition between the scrambled text and the signals which are to be transmitted and thus the unscrambled signals pass to the intermediate regenerators, and thus simpler checking of these intermediate regenerators is facilitated.

Claims (7)

1. A PCM L.d.nt. data transmission system including a transmission path extending between two end stations which transmission path is divided by intermediate 5 stations into a plurality of transmission sections, each said station being arranged to relay a sequence of individual t.d.m. signals having a periodic frame arrangement and being transmitted via said transmission path, a scrambler in each of said intermediate stations being arranged such that when no signal sequence is received by that intermediate station from one of the adjacent transmission sections, a pseudo-random sequence continuously produced by the scrambler is used to provide a signal transmitted via the adjacent transmission 15 section to which said one transmission section is to be connected by the intermediate station.
2. A system as claimed in Claim 1 wherein in each intermediate station the transmitting end includes an EXCLUS IVE-OR' gate connected as a modulo-2 adder one input 211 of which is constantly fed wi th tiie pseudo-random sequence from tho scrambler and another input of which is fed with the bit sequence which is to be transmitted, and the receiving end includes an identical scrambler for descrambling and which is arranged to be disconnected 25 during realignment.
3. A system as claimed in Claim 2 wherein each slat.ion is arranged to interpose a monitoring signal at regular intervals into the sequence of t.d.m. signals being transmitted and the scrambler is arranged to scramble 30 the monitoring signal, the scrambler being arranged to be set at a predetermined time in the periodic frame 419 62 13 arrangement of the transmitted signal so as to be in a predetermined state at Lhe beginning of the monitoring signal so that the latter is always scrambled in the same predetermined manner, and wherein the descrambler is arranged to be set at the same time as said scrambler and for monitoring the scrambler each intermediate station includes at the receiving end a circuit arrangement which compares the received deserambled monitoring signal with a signal sequence produced in said receiving end, and during realignment compares the received, scrambled monitoring signal with a predetermined signal sequence produced in said receiving end and to which should correspond said scrambled monitoring signal.
4. A system as claimed in any one of the preceding Claims wherein the scrambler comprises a shift register.
5. A system as claimed in Claim 4 wherein the scrambler comprises an eight-stage shift register in which feedback is provided from the outputs of the first, third, fifth and eighth stages to the input. 0. A system according to Claim 4 or Claim 5 wherein said shift register has a number of stages equal to the number of bits in the monitoring signal.
6.
7. A t.d.m. data transmission system substantially as herein described with reference to the accompanying drawing.
IE2659/75A 1974-12-19 1975-12-05 Improvements in or relating to data transmission systems IE41962B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742460234 DE2460234B2 (en) 1974-12-19 1974-12-19 REPLACEMENT PULSE GENERATOR

Publications (2)

Publication Number Publication Date
IE41962L IE41962L (en) 1976-06-19
IE41962B1 true IE41962B1 (en) 1980-05-07

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ID=5933904

Family Applications (1)

Application Number Title Priority Date Filing Date
IE2659/75A IE41962B1 (en) 1974-12-19 1975-12-05 Improvements in or relating to data transmission systems

Country Status (8)

Country Link
JP (2) JPS5188118A (en)
BE (1) BE836880R (en)
DE (1) DE2460234B2 (en)
DK (1) DK145838C (en)
GB (1) GB1528900A (en)
IE (1) IE41962B1 (en)
IT (1) IT1054678B (en)
LU (1) LU73830A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018453A1 (en) * 1979-05-02 1980-11-12 THE PLESSEY COMPANY plc Synthesis arrangements for use in digital data transmission systems
JPS61169048A (en) * 1985-01-21 1986-07-30 Nippon Telegr & Teleph Corp <Ntt> Digital repeater
CA1251583A (en) * 1985-03-28 1989-03-21 Yoshiaki Yato Multiplex system
JPS61255142A (en) * 1985-05-08 1986-11-12 Nec Corp Bit addition device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843209A (en) * 1971-10-01 1973-06-22
JPS5532060B2 (en) * 1973-01-17 1980-08-22

Also Published As

Publication number Publication date
DE2460234A1 (en) 1976-06-24
JPS5859250U (en) 1983-04-21
DK145838B (en) 1983-03-14
JPS5188118A (en) 1976-08-02
LU73830A1 (en) 1976-06-11
IE41962L (en) 1976-06-19
GB1528900A (en) 1978-10-18
DK145838C (en) 1983-09-05
DK577175A (en) 1976-06-20
IT1054678B (en) 1981-11-30
BE836880R (en) 1976-04-16
DE2460234B2 (en) 1976-12-02

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