JPS59245A - Digital signal processing device - Google Patents

Abstract

PURPOSE:To reduce distortion of an analog reproducing output in case when an error is propagated, by providing each 1 group of delay means for delaying the same delay quantity, before a scrambler and behind a descrambler, respectively. CONSTITUTION:A signal of an analog signal source 1, which is digitized by an A/D converter 2 is supplied to a word delaying circuit 18. In the circuit 18, a signal word is delayed every other frame by 2N frames (N is an integer of a period corresponding to 1 word portion). Thereafter, it is transmitted to a transmission line 6 through a signal processing circuit 4 and a modulator 5. In the receiving side, the signal processed by a demodulator 7 and an error detecting and correcting circuit 8 is distributed 20 to each channel, and thereafter, is applied to a word delaying circuit 21 through a descrambler 9. In the circuit 9, a signal word of a signal frame except the signal word of the signal frame which is delayed by the circuit 18 is delayed by 2N frames. In this way, even if an error is propagated and an error occurs continuously, it can be dispersed in time series mode, and distortion of an analog reproducing output can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital confidential communication device, and in particular to a digital signal processing device MK- suitable for dispersing continuous signal errors caused by private communication and reducing distortion of analog playback output. .

In general, in a communication device that converts an analog signal into a digital signal and transmits the converted signal, if it is desired to provide confidentiality to the transmitted information, an exclusive OR (CEx -0R) of a digital data string and a pseudo-random bit string is taken. A method is adopted in which a so-called double-digit operation is performed to transmit the data, and on the receiving side, the correct digital data string is reproduced by a descrambling operation that is the reverse of that on the transmitting side. Figure 1 is a block diagram showing an example of this digital confidential communication device. It is a diagram. In FIG. 1, l is an analog signal source,
2 is a noise suppressor, 3 is a scrambler, 4 is a signal processing circuit that adds a synchronization signal and a logic for detecting and correcting false alarms, 5 is a modulator, 6 is a transmission path, 2 is a demodulator, and 8 is an error detection circuit. In the correction circuit, D9 is a descrambler, 10 is a converter, and 11 is an analog signal output terminal. The signal from the analog signal source 1, which has been converted into a digital signal by the digital converter 2, is encrypted by the scrambler 3 and transmitted to the transmission line 6 via the signal processing circuit and modulator 5. On the receiving side, the signal processed by the demodulator 1 and the error detection/correction circuit 8 is decoded by the descrambler 9, the original digital signal is extracted, and the converter converts the log to the analog signal. Transmission is performed by converting. Therefore, confidentiality can be maintained by keeping the scramble and descramble operations secret from third parties.

FIG. 2 is a diagram showing an example of the scrambler 3 and descrambler 9). In FIG. 2, lji.

13, 15 and 16 are EX-OR gates, and 14 and 1f are shift registers having the same number of stages.

The scrambler 3 and descrambler 90 input/output data strings are 'm, B7FL, 'yx, and D, respectively.
Otoshi! , +OR game) Assuming that inputs 13 and 16 are taken from the outputs of the first and second stages of shift registers 14 and 11, respectively, their relationship is expressed by the following equation.

Brn= A, l■Brn= ■BnL-n ・
...+11Dni = C, S e C1j
■ C8... (2) However, the symbol ■ indicates addition by EX-OR (mad2 addition).

Here, if there are many transmission errors in the signal that has passed through the error detection and correction circuit 8, then B, l = Cゎ, so =
A,! ■B□-)OBm-n■B-jΦ~4== Am
The descrambled data sequence D□ becomes the original Noah'-II sequence Am, and encryption and decoding are achieved.

In order to increase the degree of this encryption operation and prevent a third party from decoding it, the number of stages of the shift registers 14 and 1 may be increased. Usually, this value is set to several times the number of pits representing one sample, ie, the number of bits of the l signal word.

However, as the number of stages of the shift registers 14 and 11 increases, the period during which consecutive errors occur in the output after descrambling becomes longer when a transmission error occurs.9 In other words, the bit where the igb was The period until it passes through register 1 is expressed by the formula (+1, (21υ). As is clear, Dl and J4m are not equal, and the error propagates. Therefore, during this period, in other words, several consecutive Since the error propagates to the sample signal word, even if the erroneous sample word is corrected by holding the previous value, average value interpolation, etc., a large distortion will occur in the analog signal obtained by converting it into 4 μ.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing device that eliminates the drawbacks of the prior art described above and can reduce distortion in analog reproduction output when a transmission error υ occurs and the error propagates.

To achieve this objective, the present invention provides data words for one sample (l word for a mono signal, two words for stereo, four words for 4D stereo, etc.) for one signal frame (multiple words for multi-channel transmission). signal frame with data words of l samples for each channel)
Configure the tube. This continuous frame sequence is alternately delayed by an even number of frames every other frame on the transmitting side and the receiving side, and the transmitting side performs scrambling after the delay, and the receiving side performs descrambling as a late penalty, thereby preventing pb propagation. 2) Distortion of the analog playback output is reduced by dispersing the consecutive code errors that occur so that the samples are not consecutive in time series.

The present invention is also effective when performing independent scrambling for each channel for the purpose of confidential communications between channels in the case of multi-channel transmission.Hereinafter, one embodiment of the present invention will be described. This will be explained with reference to FIGS. 5 and 4. FIG. 3 is a block diagram showing an embodiment of the present invention, 18 and 21 are word delay circuits, 19 is a multiplexer, 20 is a demultiplexer, and the bacteria 1
The same reference numerals as in the figure indicate the same thing. Word delay circuit 18
and 21 perform operations for delaying odd sample words on the transmitting side and delaying even sample words on the receiving side, respectively. The multiplexer 19 time-division multiplexes the signals of each channel scrambled by the souffles 72-3, and forms a signal frame consisting of one sample for each channel. Further, the demultiplexer 20 distributes the sample words of each channel in the time-division multiplexed signal frame to the descrambler 9 of a predetermined channel.

FIG. 4 shows word delay circuits 18 and 21 according to the present invention.
This is a diagram showing a specific example, in which 22 and 25 are serial-to-parallel conversion circuits that convert sample words from serial to parallel, 24 and 2F are parallel-to-serial conversion circuits, and 23 and 26 are delay circuits with equal delay amounts. It is.

The present invention will be explained in detail below with reference to FIGS. 3 and 4.

Digitalized analog signal source l
The signal is sent to the serial/parallel converter circuit 2 of the word delay circuit 1B.
Enter 2. The serial/parallel conversion circuit 22 converts the digital signal from 2 words in series to 2 words in parallel every 2 words.

Of the sample words converted in parallel, the first half words are passed through a delay circuit 25 having a delay amount equal to an integer (N) times the length of time for one word, and the second half words are directly processed.
The signal is input to the parallel-to-serial conversion circuit 24. Parallel-serial conversion circuit 24
Then, the 2-word parallel digital signal is converted into a serial signal and sent to the scrambler 3. The scrambled signal is time-division multiplexed with the signals of other channels by the multiplexer 19, and a signal frame is constructed in which each frame of Vcl sample words is distributed. Here, the signal word of one channel of each successive signal frame is delayed by every other frame. The signal processing circuit number under V is transmitted to the transmission line 6 via the modulator 5. A signal for identification is multiplexed into a signal frame made up of delayed samples.

On the receiving side, the signal processed by the post-adjuster IF4 detection and correction circuit 8 is distributed to each channel by a demultiplexer 2°. The signals distributed to each channel are descrambled by the descrambler 9 and input to the serial/parallel conversion circuit 25 of the word delay circuit 21. In the word delay circuit 21, referring to the identification signal multiplexed on the received signal frame, the sample word delayed on the transmitting side is transferred to the first half of the serial/parallel conversion circuit 25 (the side where the delay circuit is not included in the output). Parallel to serial conversion circuit 2'
Send to F. At this time, the first half words of the serial/parallel conversion circuit 25 are sent directly, and the latter half words are sent via the delay circuit 26, so the output of the parallel/serial conversion circuit 27 is in the original chronological order. .

The signal restored to the chronological order is outputted back to an analog signal by the example A converter 10.

Here, as mentioned earlier, if an error occurs during transmission,
Let us consider a case in which the descrambler 9 propagates consecutive errors. The input/output words of the descrambler 90 are processed by the word delay circuit 18... (41 Zuhe Tori 3-Chapter 45)
- To the thieves... They are lined up in order. Therefore, if the delay amount N is set to 2 or more, consecutive samples in chronological order will not be adjacent to each other. (For example, when N=2...q
-to &-141,6...) Even if an error propagates to the descrambler 9, the delay amount N is selected as long as the length is finite as the length of the shift register 1. Especially,
Consecutive code errors can be dispersed into samples that are not consecutive in time.

Therefore, even if a number word becomes incorrect due to error propagation, if the chronological order is restored, words without errors can be output at least before and after the incorrect word. By performing correction by means of average value interpolation, it is possible to minimize the distortion generated in the analog playback output.

According to the present invention, even if errors occur in the transmission path and propagate to cause continuous errors, these can be dispersed in time series, which is effective in reducing distortion of analog playback output. It has a big effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional digital confidential communication device, FIG. 2 is a diagram showing an example of a scrambler and a descrambler, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 2 is a diagram showing a specific example of a word delay circuit according to the present invention. 1ξ21...Word delay circuit 19...Multiplexer 20...Demultiplexer 2 birds 25...Serial to parallel conversion circuit 2426...Delay circuit 242 F...Parallel to serial conversion circuit i1 Figure

Claims (1)

[Claims] In a digital signal processing device that transmits and receives digitized single-channel or multi-channel stereo or monaural audio signals, a signal frame is constructed from stereo or monaural audio signals of one sample per channel, and the transmitting side The signal is transmitted independently for each channel through a scrambler, and on the receiving side, the signal is polarized by reproducing the original signal through a descrambler for each channel.
and a first delay means that alternately delays the time-series signal words by 1, that is, the signal words of consecutive signal frames by an even number of frames every 17 frames, and 7 frames of the signal delayed by the first delay means. a set of second delay means for delaying signal words of a signal frame other than the signal words of the first delay means by the same delay amount as the first delay means; and a digital signal processing device disposed after the descrambler.