JPH048029A - Ciphering and coding device - Google Patents

Abstract

PURPOSE:To enhance the secrecy, to apply low speed processing to a ciphering section, to miniaturize the hardware and to reduce the cost by using a cryptographic key so as to cipher only an initial value in the coding system and transmitting a resulting data. CONSTITUTION:A data compressing means B consists of a compressor 2 compressing an 8-bit digital signal into a 4-bit code and compresses a signal converted by a signal conversion means A by the coding system and the result is transmitted. A ciphering means C ciphers only an initial value by using a 64-bit key decided in secrecy between a sender and a receiver in advance. Since the initial value corresponds to an initial value at every scanning line or one over several scanning lines in the case of a television signal, the secrecy is kept by ciphering only the initial value of the coding data by using the cryptographic key.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an encryption/coding device, and particularly to an encryption/coding device for digitally transmitting audio, image signals, and the like.

[Conventional technology]

In recent years, images have become increasingly high-definition, and for example, television images that we use on a daily basis are shifting from the NTSC system to the high-definition system. When recording such high-definition images on recording media such as tapes and disks, or transmitting them to remote locations via satellites, optical fibers, cables, etc., S
Considering image quality deterioration factors such as /N and jitter, digital transmission is more advantageous than analog transmission.

On the other hand, while digital transmission has the advantage of not causing deterioration in image quality no matter how many times dubbing is repeated in recording systems such as tapes and disks, illegal copying and duplication pose a major social problem. We also provide communication services such as satellites, optical fibers, and cables.
In the broadcasting system, there is a problem in that people who have not paid their fees or people outside the party are able to watch and listen to the content in secret.

Therefore, in conventional digital transmission, when transmitting data from a computer or the like, a method has been used in which all the data is encrypted before being sent, and the receiving side decrypts it using an encryption key.

Next, a conventional example of hard encryption will be explained using FIGS. 12 and 13.

Figure 12 is from FIPS Publication 4 dated January 15, 1977.
The US data encryption standard disclosed in
encryption 5 standard ;hereinafter DES
FIG. 13 is a diagram showing the encryption function of FIG. 12.

This conventional data encryption algorithm has been published as the "Data Encryption Standard" as described above.

This DES (conventional example) will be explained below with reference to FIGS. 12 and 13.

First, DES is a block cipher for binary data consisting of 0 and 1. In DES, binary data is divided into 64-bit blocks, and each block is encrypted by repeating transposition and the upper half. The key is 64 bits, of which 8 bits are check bits for error detection, and 56 bits are valid. This key controls the first half of each round. Figure 12 of the drawing is DES
The process of encryption is shown. Moreover, FIG. 13 shows a function fK(R) which is the central part of encryption.

In Figure 12 of the drawing, the 64-bit plaintext is first transposed. This is a fixed transposition that is independent of the key. Next, the 64 bits are divided into a left half L0 and a right half R0.

After that, Ln=R, over 16 stages.

Ro” L n-+ + f K. (Ro-1))
The operation "0)" is repeated. Here, + represents the sum of m0d2 for each hit. Also, Lo.

R, is the left half of 3 when the nth stage operation is completed.
2 bits and the right half 32 bits.

K is constructed from the key as shown on the right side of FIG. In FIG. 12, SI+..., S]6 is 1 or 2. Further, reduced form transposition 2a is transposition excluding some of the inputs. In this case, 8 bits out of 56 inputs are removed, resulting in 48 bits of output. Reduced form transposition is an irreversible transformation, meaning that the input cannot be completely restored from the output. This makes key estimation more difficult.

Next, the function fx(R) in FIG. 12 will be explained using FIG. 13.

In FIG. 13, in order to create the function fK(R), R is first subjected to an extended form transposition 3a. Extended transposition is a transposition that duplicates some of the inputs. in this case,
Of 32 bits of input! 6 bits appear redundantly on the output. Next, K composed of keys is added bit by bit to this output mod 2. The resulting 48 bits are divided into eight small blocks of 6 bits, and each 6 bit is converted into 4 bits by S, , S, . . . -', S8. This can be thought of as a type of upper half when 6 bits are considered as one character. However, since the output is compressed to 4 bits, this conversion is irreversible. Therefore, f(R) is generally an irreversible function. However, this does not mean that the transformation of equation (1) above is irreversible. In fact, equation (1) is
Since it can be transformed as Ln, Rn to LFL-1+R,,
It turns out that it is possible to calculate

Now, repeat the calculation of equation (1) 16 times, L, 6. R,
After finding 6, transpose the stiffness one last time to finish the encryption.

Next, decoding will be explained.

Decryption can be performed by performing almost the opposite operation of encryption.

Simply put, all you have to do is proceed from the bottom to the top in Figure 12. First, perform the inverse transposition of the last transposition of encryption, and calculate Rn-1+L n-1 using the following formula (2). Once Ro and Lo are obtained, the inverse transposition of the first transposition of encryption is performed. The original 64 bits can be obtained by transposing .

So far, there is no known way to decipher the DES ciphertext other than by keying the keys one by one. Now, suppose it takes 1 microsecond to check whether a key is the correct key. At this time, 256
It would take 2,283 years to find all the keys. Even if you are very lucky, it will take several hundred years.

(Problems to be Solved by the Invention) As explained above, in the conventional example, in the case of high definition video images such as high-definition, if an analog image signal is immediately A/D converted and transmitted, for example, , when trying to secure a video signal band of 30MHz or more,
According to the sampling theorem, sampling must be performed at a rate of at least 60 MHz, 74.25 MHz, 8
When converting bits into A/D, the transmission rate is 74.25 (
MHz) x8 (bit) = 594 (Mbit /
S). In order to save transmission capacity, the amount of information is reduced by 1.
Even if it is compressed to 15, it will be about 120 (Mbit/s
) will result in a transmission rate of Encrypting and transmitting such a huge amount of information requires high-speed processing by the encryption unit.

The problem was that it was extremely difficult in terms of hardware size and cost.

This invention was made to solve the above-mentioned problems, and by encrypting only the initial value of the encoded data using the encoding method and transmitting it, the secrecy is increased and the encryption It is an object of the present invention to provide an encryption/encoding device that performs low-speed processing in a coding section, downsizes hardware, and reduces costs.

[Means to solve the problem]

Therefore, in the present invention, there is provided a signal conversion means for converting an image/audio signal from analog to digital, a data compression means for compressing and transmitting the signal converted by the signal conversion means using an encoding method, and a data compression means for compressing and transmitting the signal converted by the signal conversion means, and The present invention aims to achieve the above-mentioned object by an encryption/encoding device comprising an encryption means for encrypting only the initial value of encrypted data using an encryption key.

[Effect]

In the encryption/encoding device of the present invention, the signal conversion means converts the image/audio signal from analog to digital, the data compression means compresses the signal using an encoding method, and the encryption means encodes the signal. Only the initial value of the data is encrypted using the encryption key and transmitted.

〔Example〕

An embodiment of the present invention will now be described based on the drawings.

FIG. 1 is a block diagram of the encryption encoding transmission system according to the first and second embodiments of the present invention, FIG. 2 is a diagram showing the transmission data format of FIG. 1, and FIG. 3 is a diagram showing the transmission data format of the first and second embodiments of the present invention. FIG. 4 is a block diagram of the code determination type decoding circuit of FIG. 3, FIG. 5 is a block diagram of the decoding device of this first embodiment, and FIG. A block diagram of the compressor in the second embodiment of the invention, FIG. 7 is a diagram showing how all pixel data is divided into pixel blocks in the second embodiment, and FIG. 8 is a diagram showing how each pixel block in FIG. 7 is divided. 9 is a diagram explaining the compressor of FIG. 6, and FIG. 9 (a
) is the state of quantization in the division value conversion section in Fig. 6, and Fig. 9
Figure (b) shows each state of decoding. FIG. 10 is a diagram showing transmission data for one pixel block, and FIG. 11 is a configuration diagram of a receiving side corresponding to the data transmitting side of FIG. 6.

As mentioned above, FIG. 1 shows an embodiment of the encryption coding transmission system of the present invention, in which 8-bit PCM data is first encrypted and transmitted as an initial value, and then, based on the initial value, FIG. 2 is a configuration diagram of an encryption encoding device that sequentially transmits 4-bit compressed data.

First, the calling side will be explained.

In FIG. 1 of the drawing, A is a signal converting means, and is an A/D converter 1 that converts a video signal into an 8-hit PCM signal.
It is a means for converting image and audio signals from analog to digital. B is a data compression means, which is composed of a compressor 2 that compresses an 8-hit digital signal into a 4-hit code, and a means for compressing the signal converted by the signal conversion means A using an encoding method and transmitting it (Details will be described later). C is an encryption means, which is composed of an encryptor that encrypts only the initial value using a 64-bit key that is secretly decided between the sender and the receiver, and as described above, the encoded data is This is a means of encrypting only the initial value of with an encryption key (details will be described later).

Further, 4 is a switch, and the initial value (first value) is encrypted according to the transmission data format shown in FIG.
5 is a parallel-to-serial converter (P/S) that converts the encrypted initial value and compressed data into serial data according to the transmission format. It is. The 1-bit serial data from the parallel-to-serial converter 5 is sent to the receiving side through the transmission line 6 in FIG. Here, the transmission path 6 is, needless to say, a recording system such as a tape or a disk, or a communication/broadcasting system such as a satellite, optical fiber, or cable.

Next, the receiving side will be explained.

In Drawing 3 @ 1, 7 is a serial/parallel converter (S/P) that converts received data into parallel data, 8 is a switch, and 5YNC according to the transmission data format shown in Fig. 2.
9 is a decryptor that decodes the encrypted initial value, and 10 is a 4 A decoder decompresses the compressed bit data into an 8-bit PCM signal using the initial value decoded by the decoder 9, and a DA converter 11 converts the 8-bit PCM data into an analog signal.
D/A).

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 11, focusing on the data compression means B and encryption means C.

First, the data compression means B and the initial values to be encrypted will be explained.

As a compression means (method) used when transmitting data obtained by sampling a signal with a large amount of information such as an image signal,
For example, the difference P CM (Pulse CodeModu
ration) method (hereinafter referred to as DPCM) is generally well known. The DPCM is a method in which the value of a sample point that is currently being encoded is predicted from the value of a sample point that has already been encoded, and the difference (prediction error) between the predicted value and the original value is encoded. For signals such as image signals where the correlation between values at adjacent sample points is large, highly efficient encoding is achieved by performing non-linear quantization in consideration of the bias in the generation distribution of prediction error signals. can be done.

As mentioned above, FIG. 3 shows the configuration of the compressor 2 in FIG. 1 that compresses 8-bit data into a 4-bit code, and FIG. 4 shows the code determination type of this encoding device. FIG. 3 is a diagram showing the configuration of a decoding circuit. Furthermore, FIG. 5 shows the configuration of a decoding device that decodes the code obtained by this encoding device.

In FIG. 3 of the drawing, 8-bit image data is input to an input terminal 101, is limited by a limiter 108 to within a predetermined range, for example 16 to 235, and is input to a subtraction circuit 102.
In this step, a difference value (forecast error) from the predicted value output from the predicted coefficient multiplication circuit 103 is calculated. This prediction error is supplied to the code multiplexing type quantization circuit 104. In the quantization circuit 104, the 9-bit prediction error data including signs indicating positive and negative is converted into 4-bit prediction error data based on the quantization characteristic in which the positive and negative are superimposed and assigned the same sign, as illustrated in Table 1 below. The signal is quantized and outputted from an output terminal 105, and also supplied to a sign judgment type decoding circuit 106.

Table 1 The quantization characteristics shown in Table 1 are an example of a table that uses past decoded values to determine whether the prediction error is positive or negative and selects one representative value for prediction errors that take values between -219 and 219. By assigning one 4-bit sign to each of the positive and negative quantization steps, 5 is obtained.
This enables encoding with a number of quantization steps equivalent to bits.

This table is set so that the two divided regions, positive and negative, assigned to the same code have a level difference corresponding to the limited dynamic range of decoded values (for example, 220), and the lower end of the region is set as the quantization representative. Since the decoding results are of an undershoot type, the positive and negative representative values have a level difference of 220, and only one of them always falls within the dynamic range (0 to 219). This makes it possible to determine whether the difference value is positive or negative, as will be described later.

Further, in the case of an image signal, a difference value near 0 is important, and in order to realize superposition of nonlinear characteristics, both positive and negative signals have a symmetrical structure folded back at the center.

The code determination type decoding circuit 106 (FIG. 3) decodes the code output from the quantization circuit 104 using the predicted value that is the output of the prediction coefficient multiplication circuit 103, and supplies the decoded value to the delay circuit 107. do. After the decoded value is delayed by a predetermined period (for example, one sample period) in a delay circuit 107, it is multiplied by a prediction coefficient in a prediction coefficient circuit 103 and is supplied as a prediction value to the subtraction circuit 102 and the sign judgment type decoding circuit 106. .

Here, the operation of the sign determination type decoding circuit 106 shown in FIG. 3 will be explained using FIG. 4. In Figure 4 of the drawing, terminal 20
The 4-bit code output from the code-multiplexed quantization circuit 104 is input to 1, and the + side representative value setting circuit 20
2 and the − side representative value setting circuit 203. The typical positive and negative output values of the circuits 202 and 203 are as follows:
In each of the adder circuits 205 and 206, the terminal 20
4 are respectively added to the predicted values supplied from 4, and are supplied to the selection circuit 207 as positive and negative decoded values.

The outputs of the representative value setting circuits 202 and 203 are always “
Since the level difference of 220" is maintained, the selection circuit 207
The positive and negative decoded values supplied to the
255″) limited dynamic range “1
6 to 235". Therefore, by selecting the positive or negative decoded value within the range, the correct decoded value can be obtained from the code multiplexed input. Therefore, from the + side adder circuit 205. The level of the output decoded value data is compared with a threshold value "236" by the comparator 209, and the output signal controls the selection circuit 207 to select a positive or negative decoded value and output it from the terminal 208.

Here, the code determination operation in this embodiment will be explained using a specific example. Now, consider a case where the predicted value is "100" and the current input value is "150". The prediction error is “+5”
0", the code multiplexing type quantization circuit 104 outputs "5" as 4-bit quantized value data as shown in Table 1. The code determination type decoding circuit 106
, the + side decoded value data is "136" and the - side decoded value data is "-84", so "136", which is within the appropriate dynamic range, is selected as the decoded value.Similarly, the current input value is "50" and the prediction error is "-50", the output of the quantization circuit 104 is "11". In this case, the + side decoded value data is "284" and the - side decoded value data is "64". Therefore, "64", which is within the appropriate dynamic range, is selected.

Next, a decoder for decoding the code encoded and transmitted by the compressor shown in FIG. 3 will be explained using FIG. 5.

In FIG. 5 of the drawing, a 4-bit code encoded by the encoding device (compressor) is input to an input terminal 301 and supplied to a + side representative value setting circuit 302 and a − side representative value setting circuit 303. be done. The positive and negative representative values that are the outputs of the circuits 302 and 303, respectively, are added to the adder circuits 304 and 3.
05, respectively, are added to the predicted values supplied from the prediction coefficient multiplication circuit 309, and are supplied to the selection circuit 306 as positive and negative decoded values. Representative value setting circuit 302
, 303 always maintain a level difference of "256" due to the characteristics of the codes, so the selection circuit 30
One of the positive and negative decoded values supplied to 6 is always outside the limited dynamic range "16-235".

Therefore, by selecting the positive or negative decoded value within the range, the correct decoded value of the code can be obtained. Therefore, the decoded value outputted from the + side adder circuit 304 is compared with the threshold value "236" by the comparator 310, and the selection circuit 306 is controlled by the output to select one of the positive and negative decoded values. The decoded value of the bit is output from the output terminal 307. Further, this decoded value is supplied to a delay circuit 308, delayed by one sample period, and sent to a prediction coefficient multiplication circuit 309. The prediction coefficient multiplication circuit 309 calculates a prediction value by multiplying the delayed decoded value by the prediction coefficient, and supplies the predicted value to each of the addition circuits 304 and 305 in order to decode the later input code. A decoder can be realized with the above configuration.

As explained above, the differential PCM (DPCM) method is a system that quantizes and transmits the difference values of adjacent sample points, so if the initial value is uncertain, it is completely impossible to restore subsequent sample points. It can be seen that usually,
In the case of television, this initial value is given every scanning line or every fraction of a scanning line, so secrecy is maintained by encrypting only the initial value of this encoded data with an encryption key. dripping

Next, an encryption/encoding apparatus which is a second embodiment of the present invention will be described with reference to FIGS. 6 to 11.

In this second embodiment, the encoding method of the data compression means is a block encoding method, and only the initial value of the encoded data is encrypted using an encryption key.

The above block encoding method divides all pixels constituting a screen into pixel blocks each consisting of a plurality of pixels, and transmits a pair of data regarding the maximum value and minimum value among all pixel data in each pixel block. At the same time, pixel data quantized based on the pair of pixel data is transmitted.

FIG. 6 is a diagram showing the configuration of an image transmission system according to the second embodiment. In FIG. 6, 601 is a terminal into which n-bit digital image data obtained by sampling a raster-scanned analog image signal such as a television signal at a predetermined frequency and digitizing it is input. This 2°
The gradation digital image data is obtained by the pixel block extraction unit 602.
supplied to FIG. 7 is a diagram showing how all pixel data is divided into pixel blocks. Pixel block cutting section 60
2, as shown in Figure 7, 1 pixel in the horizontal direction (hereinafter referred to as the H direction) and m in the vertical direction (hereinafter referred to as the V direction)
A pixel block consisting of (UXm) pixels is cut out. That is, the data of each extracted pixel block is output.

FIG. 8 shows the configuration of each pixel block. In the figure, D3,1
~Dm and Ji indicate each pixel data. The image data output from the pixel block extraction section 602 is sent to the maximum value detection section 603. The signal is input to a minimum value detection section 604 and a timing adjustment section 605. As a result, among all the pixel data (D+, + to Dm, z) in each pixel block, the one with the maximum value (Dll1ax) and the one with the minimum value <7)
(Dmin) l)'; Detected by each of the detection units 603 and 604 and output.

On the other hand, in the timing adjustment section 605, the maximum value detection section 603 and the minimum value detection section 604 calculate Dmax, D
All pixel data is delayed for the time necessary to detect min, and the pixel data is sent to the divided value converter 606 in a predetermined order for each pixel block. For example, for each pixel block DI+l+D 2.11 D 3+l +++
+++I) m, + + D 112-・= D L2
+””-D+,〈p-++-Dm,tt-I)D
+, 1-Di, i, and so on.

In this way, all pixel data (D +
+I −Dm, M ) and their maximum value (D ma
x) and the minimum value (D fi+in) are divided value converter 6
06, each pixel data is input to D max and D wi
Compare n with the quantization level divided into 2 and obtain the bit division code (Δl + I ~ Δ text) 6゜Here, k
is an integer smaller than n, and its quantization is shown in FIG. 9(a).

As shown in FIG. 9(a), Δi,j are output as binary bit codes. The n-bit division code Δi, j obtained in this way and the n-bit D alax and D w
in is a parallel-to-serial (p-s) converter 607, respectively.
, 607a, and 607b, and the data selector 608 converts the data into serial data as shown in FIG. Note that FIG. 10 shows transmission data for one pixel block.

The data output from the data selector 608 (FIG. 6) is stored in a fast-in-fast-out memory (FIFO-
First-come, first-served basis) At 609, the data is subjected to time axis processing so as to have a constant data transmission rate, and then a synchronization signal is added by a synchronization adding section 610, and the data is sent from an output terminal 611 to a transmission path (for example, a magnetic recording/reproducing system such as a VTR). Ru. Here, the synchronization signal may be added for each pixel block or for each plurality of pixel blocks. Note that the operation timing of each of the above-mentioned sections is determined based on a timing signal output from the timing control section 612.

FIG. 11 shows the configuration of the receiving side corresponding to the data transmitting side shown in FIG. In Figure 11, 621
is a terminal to which the transmission data encoded with high efficiency on the transmission side described above is input. A synchronization signal in the input transmission data is separated by a synchronization separation section 622 and supplied to a timing control section 623. The timing control section 623 determines the operation timing of each section on the receiving side based on the synchronization signal.

On the other hand, the data selector 624 divides the aforementioned transmission data into n-bit data Dmax, Dmin and codes Δi, j obtained by bit quantizing each pixel data between Dmax and Dtnrn. This is converted into parallel data by respective serial-to-parallel (s-p) converters 625 and 625a, respectively. sp converter 6
The maximum value data Dwax and minimum value data Dakin in each pixel block, which are set as parallel data in 25, are latched by latch circuits 626 and 627, respectively, and the latched maximum value data Dax and minimum value data Dmin are respectively latched by latch circuits 626 and 627. It is output to the divided value inverse transformer 628. On the other hand, the division code Δi for each pixel data in each pixel block
, j are the sp converters 625a in a predetermined order as described above.
, and is supplied to the divided value inverse transformer 628 .

FIG. 9(b) shows division codes Δi, j and Dmax.

Representative value data D' related to the original pixel data from D win
This is a diagram showing how to decode i and j, as shown in the diagram,
The representative value is set, for example, to the middle of each quantization level obtained by dividing Dmax and Dmin into two. The n-bit representative value data (D
'+, + to p's, x) are output for each pixel block in the above order. Scan converter section 62
9 (FIG. 11), the output data of the divided value inverse conversion section 628 is converted by a scan converter section 629 in an order corresponding to raster scanning, and is outputted to an output terminal 630 as decoded image data.

As explained above, in the block encoding method,
If either the maximum value and/or the minimum value, which are the initial values, are indefinite, it is completely impossible to restore the sample points within that block. Confidentiality is maintained by encrypting only the initial value of this encoded data using an encryption key.

(Effects of the Invention) As explained above, according to the present invention, by encrypting and transmitting only the initial value in the encoding method using the encryption key, secrecy is high, the encryption part is processed at low speed, and the hardware is This has the effect of making it possible to provide an encryption/encoding device that is smaller in size and lower in cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encryption encoding transmission system according to the first and second embodiments of the present invention, FIG. 2 is a diagram showing the transmission data format of FIG. 1, and FIG. 3 is a diagram showing the transmission data format of the first embodiment of the present invention. FIG. 4 is a block diagram of the code judgment type decoding circuit in FIG. 3, FIG. 5 is a block diagram of the decoding device in the first embodiment, and FIG. 6 is a block diagram of the decoding device according to the first embodiment. A block diagram of the compressor in the second embodiment, FIG. 7 is a diagram showing how all pixel data is divided into pixel blocks in the second embodiment, and FIG. 8 shows each pixel block in FIG. 7. 9A and 9B are diagrams for explaining the compressor of FIG. 6, and FIG. 9(a) shows the state of quantization in the division value converter of FIG.
b) shows each state to be decoded. Figure 10 is 1
Figure 11 showing transmission data for two pixel blocks.
The figure is a configuration diagram of the receiving side corresponding to the data transmitting side in Figure 6,
FIG. 12 is a block diagram showing conventional encryption, and FIG. 13 is a diagram showing the encryption function of FIG. 12. A-...Signal conversion means B...Data compression means C...Encryption means 1...-A/D 2-----Compressor 3... Encryptor 6 Transmission line 9 Decoder 10 Decoder Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] Signal conversion means for converting an image/audio signal from analog to digital; data compression means for compressing and transmitting the signal converted by the signal conversion means using an encoding method; and the encoded data. An encryption encoding device comprising: an encryption means for encrypting only the initial value of using an encryption key.