JPS58218253A - Digital signal processor - Google Patents

Abstract

PURPOSE:To decentralize successive code errors and to reduce the distortion of an analog reproduction output in case of a transmission error, by delaying a data string with a specific interval on a transmission and a reception side alternately. CONSTITUTION:A signal from an analog signal source 1 is converted by an AD converter 2 into a data string, which is delayed, word by word, through a word delay circuit 18. The output of the circuit 18 is applied through a scrambling circuit 3 to a signal processing circuit 4, which adds synchronizing bits and error correcting bits to the signal, sending the resulting signal from a modulator 5 to a transmission line 6. The signal from this tansmission line 6 is applied to a word delay circuit 19 through a demodulator 7, error correcting circuit 8, and descrambler 9. Words which are not delayed on the transmission side are delayed by the circuit 19 and successive code errors are decentralized to reduce the distortion of the analog reproduction output in case of an error of transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital confidential communication device, and more particularly to a digital signal processing device suitable for dispersing continuous signal errors caused by confidential communication and reducing distortion of analog playback output.

In general, in a communication device that converts an analog signal into a digital signal and transmits it, if you want to make the transmitted information confidential, you must perform a so-called scrambling operation that takes an exclusive OR of a digital data string and a pseudo-random bit string. In the receiving example, the original digital data is recovered by the reverse operation, that is, the descrambling operation, on the sending side. I can't find a way to play it.

FIG. 1 is a block diagram showing an example of this digital confidential communication device. In the figure, 1 is an analog signal source, 2 is an AD converter, 3 is a scrambler, 4 is a signal processing circuit that multiplexes synchronization bits and parity bits for error correction, 5 is a modulator, 6 is a transmission line, and 7 is a demodulator; 8 is an error correction circuit;
9 is a descrambler, 10 is a DA converter, and 11 is an analog signal output terminal. Its operation is to encrypt transmission information converted from analog to digital by a scrambler 3 and transmit it, and on the receiving side, it is decoded by a descrambler 9 to extract the original information. Therefore, confidentiality can be maintained by keeping the scramble and descramble operations secret from third parties. FIG. 2 is a circuit diagram showing an example of the scrambler 23 and the descrambler 9. 12, 13. 15 and 16 are FOR,
Both circuits 14 and 17 are shift registers having the same number of stages.

Here, suppose that the input/output data strings of the scrambler 3 and descrambler 90 are 2~'' + Bm + Cm and Hori, and the outputs of the shift registers 1, 4, and 17 are taken from the nth stage and the first stage. The relationship is shown by the following formula: 1 1 Bm-j'% Brrl-n (1) Ya=.

,. -, 11□ -0,2° However, the symbol ■ indicates goR1g calculation (mod 2 addition).

Assuming that the error correction circuit 8 operates as expected and there is no transmission error, Bm = Cm, so On = A.
m■Bn-j■Bin-n■Bm-j■Bm-n=A
m (3n..., B■B30), the descrambled data string Dm becomes the same as the original data string Am before scrambling, and the encryption and decryption operations are accomplished.

This encryption operation? To make it more sophisticated and prevent third parties from decoding it, the number of shift registers 4 and 170 may be increased. Usually, this value is set to several times the number of bits representing one sample value, ie the number of bits of one signal word.

But a shift register with 4 and 170 stages? The more transmission errors occur, the more consecutive errors will occur in the output after decoding. The period G:f required for the pit to pass through the left register 7. As can be seen from Hiiragi (1) and (2), the length and the number are not equal. Therefore, during this period, several signal words will continue to be erroneously decoded, and a large distortion will occur in the kDA-converted analog signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing device that eliminates the above-mentioned conventional drawbacks and reduces distortion of analog playback output when a transmission error occurs.

This purpose? To achieve this, the present invention consists in dispersing continuous code errors by alternately delaying regularly spaced data sequences, so-called signal words, on the transmitting side and the receiving side, thereby reducing distortion in the analog reproduction output.

FIG. 6 is a block diagram showing one embodiment of the present invention.
8 and 19 indicate the word delay circuit 20, which is an average value interpolation circuit, and the same reference numerals as in FIG. 1 indicate the same components.

The word delay circuits 1B and 19 perform an operation of alternately delaying a data string of a fixed length, for example, a bit string representing a -sample value, that is, one word, on the sending side and the receiving side. When a code error occurs, the average value interpolation circuit 20 calculates an average value from data before and after the code error, outputs it, and performs interpolation. Is this invention the following? Figure 4? This will be explained in detail using

FIG. 4 is a block diagram showing a specific example of the word delay circuit according to the present invention, in which 21 and 27 are serial-to-parallel conversion circuits for data strings, 22 and 28 are parallel-to-serial conversion circuits, and 2!1 ,24°25.26.29,50.5
1 and 32 indicate delay devices having equal delay times, respectively.

The serial-to-parallel converting circuits 21 and 27 convert the data manually input in series into a plurality of parallel data units, and conversely, the parallel-to-serial converting circuits 22 and 28 convert these parallel data into serial data.

Convert. Delay device 25.24, 25.26.29.30
．． The delay times 51 and 32 are an integral number (N) times the period corresponding to one word, and the number of words to be converted in parallel.

It is set to an integral multiple of (8 in FIG. 4).

The transmitting side word delay circuit 18 delays even-numbered words and also changes the order of the words. Receiving side word delay circuit 1? So, what about the operation of delaying the words that were not delayed on the sending side and restoring the word order? do.

As mentioned above, if consecutive code errors occur in the output of the descrambler 9 due to a transmission error, the serial-to-parallel conversion circuit 27 converts it directly into parallel data, but there is a delay and order switching operation. Parallel by −
Code errors are distributed in the output of the serial converter.

In other words, error-free data is output at least before and after the erroneous data. Therefore, if the average value interpolation circuit 20 interpolates the erroneous portion, the analog playback output will not suffer from the large distortion that occurs in the conventional case.

As described above, according to the present invention, even if continuous code errors occur due to transmission errors, they can be dispersed, which is effective in reducing distortion of analog playback output.

[Brief explanation of drawings]

Figure 1 shows a conventional digital: secret communication device.
Oh,. 511, @21N・:□□i, 5, a circuit diagram showing an example of a kerater and a descrambler, FIG. 3 is a block diagram showing an example of the present invention, and FIG. 4 is a word delay circuit diagram according to the present invention. FIG. 2 is a block diagram showing an example of a circuit. 18.19... Word delay circuit, 20... Average value interpolation circuit, 21.27... Series-parallel conversion circuit, 22.28...
・Parallel-serial conversion circuit, 23.24.25.26.29
．． 30.31.32...Delay device. Agent Patent Attorney Usui 1) Desk g', j19:, A,, 1
(Fig. 1)

Claims (1)

[Claims] In a communication device that transmits and receives digitized acoustic signals, 1. The signal is transmitted through a scrambler, and on the receiving side, the original signal is regenerated through a descrambler to polarize it, and the time-series signal words are alternately transmitted, that is, the signals adjacent to each other before and after any given signal are transmitted. a first delay means for delaying the word to a signal frame other than the arbitrary signal 7'-4; and a signal word other than the signal word delayed by the first delay means. A set of second delay means for delaying the first delay means by the same amount of delay is provided, and the set of second delay means are arranged before the scrambler and after the descrambler, respectively. Digital signal processing equipment.