KR970008301B1 - Signal framer and reframer of optic communicator system - Google Patents

Abstract

A signal framer and reframer of an optical transmission system transmits a maintenance data between the subscriber connection/terminals by using 16-bit unit, thereby achieving a mass data transmission. The signal framer includes: a frame word/control signal generator(1) for receiving a predetermined clock, and generating a frame word(11101000(OxE8)) and a predetermined control signal; a data latch(2) for latching an external input predetermined data according to an external input control signal(WR*,M_ADIS*,S_ADIS*); first and second converters(3,4) for receiving control signals from the generator(1), and converting a latched data in the latch(2) to a serial data by a predetermined bite; and OR gate(5) for performing OR operation about the frame word from the generator(1) and the data from the converters(3,4).

Description

Signal framers and leaf reamers in optical transmission systems

1 is a structure diagram of a 64Kb / s signal framer,

2 diagrammatic structure of a 64Kb / s signal leaf

FIG. 3 is a 64Kb / s signal framer and leaframer timing diagram,

4 is a configuration diagram of a frame word and a control signal generator;

5 is a timing diagram of a frame word and a control signal generator;

6 is a block diagram of a frame word detection and control signal generator;

7 is a timing diagram of a frameword detection and control signal generator.

* Explanation of symbols for main parts of the drawings

1 frame word and control signal generator 2, 8, 9 data latch unit

3,4: parallel / serial conversion unit 5: logical sum gate

6: frame word detection and control signal generator

7: serial / parallel (S / P) conversion unit 10: output unit

The present invention relates to signal framers and leaframers for signaling and maintenance data transfer between subscriber access / terminal devices in optical transmission rooms such as optical cable television (CATV) networks.

In general, 64Kb / s signal framers and leaflayers for signaling and maintenance data transmission between subscriber access / terminal devices in optical transmission networks such as conventional optical CATV networks configure and transmit frames in 64Kb / s 8-bit units. However, due to an increase in maintenance data between subscriber access / terminal devices in an optical CATV network, there is a problem in that maintenance data processing between subscriber access / terminal devices cannot be processed by an 8-bit transmission method.

Accordingly, an object of the present invention is to provide a signal framer and a leaf lamer capable of transmitting a large amount of data by transmitting maintenance data between subscriber access / terminal devices in units of 16 bits.

In order to achieve the above object, the present invention provides a frame word and control signal generating means for receiving a predetermined clock from outside to generate a frame word and a predetermined control signal, and inputted from the outside according to a control signal input from the outside. Data latching means for latching predetermined data and control signals from the frame word and control signal generating means, and the first and second P / s converting the data latched by the data latching means into serial data by predetermined bytes. And a logical sum gate for performing logical sum operation on the S conversion means, the frame word from the frame word and the control signal generating means, and the data from the first and second P / S conversion means.

In addition, the present invention provides a frame word detection and control signal generating means for receiving a predetermined clock and maintenance data from the outside to detect a frame word to generate a predetermined control signal, and from the frame word detection and control signal generating means. S / P conversion means for receiving a specific control signal and S / P conversion of maintenance data from the outside, and receiving control signals from the framer detection and control signal generating means and receiving the control signal from the S / P conversion unit. First and second data latching means for latching each 8-bit parallel data, and an output for generating an output control signal by receiving a predetermined signal input from the outside and selectively outputting data from the first and second data latching means. A means is provided.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7.

First, FIG. 1 shows a block diagram of a 64Kb / s signal framer, in which 1 is a frame word and control signal generator, 2 is a data latch unit, and 3 and 4 are parallel / serial conversion units. Denotes three-input logical sum gates, respectively.

As shown in the figure, the frameword and control signal generator 1 receives a 64 kHz clock provided by an optical cable television entertainment system (CATV NT ASIC) and receives a frameword (CNTR = 11101000 (OxE8)) and various kinds of clock signals. The detailed function and configuration for generating the control signal will be described later.

The data latch unit 2 is an 8-bit parallel data D [7: 0], a write signal WR *, a first byte enable signal M_ADIS *, and a second bind enable at the maintenance matching unit of the subscriber device. The signal S_ADIS * is received to latch 2 bytes so that the first byte is provided to the first P / S converter 3 and the second byte is supplied to the second P / S converter 4.

The first P / S converting unit 3 and the second P / S converting unit 4 transmit the first byte and the second byte provided from the data latch unit 2 from the framer and control signal generator 1. In accordance with the control signal MEN, S [2: 0], the parallel-serial converted bit string is provided to the three-input ration gate 5.

The three-input OR gate 5 is a bit string from the framer CNTR from the frame word and control signal generator 1, the first P / S converter 3 and the second P / S converter 4; And prints it. At this time, the output bit stream is transmitted to the subscriber access device through 155,520Mb / s transmission system by 1 bit in 2048Kb / s (64Kb / s * 32bits) frame unit.

2 is a block diagram of a 64 Kb / s signal leaf ramer, in which 6 is a frame word detection and control signal generator, 7 is a serial / parallel (S / P) conversion unit, 8 and 9 are data latch units, and 10 are shown in FIG. Denotes an output unit, respectively.

As shown in the figure, the frame word detection and control signal generator 6 receives the maintenance data bit string and the 64 ms clock transmitted to the subscriber access device through the 155,520 Mb / s transmission system. E8)) to generate various control signals required for the reframe while maintaining frame synchronization, and provide them to the signal processing units 7, 8, and 9, which will be described later. The S / P converter 7 receives the maintenance data bit string from the outside and converts the 8-bit parallel data by serial-to-parallel conversion into a clock CP provided by the frame word detection and control signal generator 6. Is provided to the first and second data latch portions 8 and 9. The first data latch unit 8 and the second data latch unit 9 control the 8-bit data provided from the S / P converter 7 from the framer detection and control signal generator 6. Latched to (LDH, LDH) and provided to the output unit (10). The output unit 10 outputs 8-bit parallel data provided from the first data latch unit 8 and the second data latch unit 9 according to the control signals HSEL * and LSEL * from the outside. to provide.

For reference, a timing diagram of the 64 Kb / s signal framer and the leaf lamer thus constructed and operated is shown in FIG.

4 is a block diagram of the framer and control signal generator 1 shown in FIG. 1, in which FIG. 11 is a 5-bit counter, 12 is a frame word generator, and 13 is a control signal generator.

As shown in the figure, first, the 5-bit counter 11 receives a 64 ms clock from the outside, 32 ms divided by 2, 16 ms divided by 8, 8 ms divided by 8, 4 ms divided by 32, and 32 divided by A 2 ㎑ clock is generated and provided to each of the signal processing units 12 and 13. The frame word generator 12 generates a frame word at a period of 2 ms by using the divided clock from the 5-bit counter 11 and provides it to the control signal generator 13. The control signal generator 13 receives the divided clock from the 5-bit counter 11 and generates signals MEN and SEN for controlling the timeslot to receive the maintenance signals of 8 bits each. It has a function of retiming and outputting the frame word and the divided clocks from the frame word generator 12 at the falling edge of 64 ms clock. For reference, a timing diagram of the frame word and the control signal generator configured and operated in this way is shown in FIG. 5.

6 is a block diagram of the frameword detection and control signal generator 6 of FIG. 2, in which 61 is a frameword detector and 62 is a 5-bit counter and a control signal generator.

As shown in the figure, the framer detector 61 detects the framer (OxE8) in a 2048 Kb / s frame input from the outside and generates a control signal DET when the framer is detected. Provided at 62. The 5-bit counter and the control signal generator 62 receive the control signal DET from the frameword detector 61, generate a 64 kHz clock only until 16, and output it through the CP output terminal. The terminal signal LDH maintains a logic '0' only between the 7th falling edge and the 8th falling edge of the signal, and the terminal signal LDL maintains a logic '0' only between the 15th falling edge and the 16th falling edge of the clock. It provides a function to output. For reference, a timing diagram of the generation part of the frameword detection and control signal configured and operated in this way is shown in FIG.

According to the present invention, a 64Kb / s signal frame is constructed using a general-purpose logic gate to transmit and receive 16-bit data using a serial 64Kb / s channel, that is, to maintain maintenance data between subscriber access / terminal devices. There is a distinctive effect of transmitting a large amount of data by transmitting bit by bit.

Claims (10)

Frame word and control signal generating means 1 for receiving a predetermined clock from the outside and generating a frame word 11101000 (OxE8) and a predetermined control signal, and control signals WR *, M_ADIS * and S_ADIS input from the outside. Data latching means (2) for latching predetermined data input from the outside according to *) and control signals from the framer and control signal generating means (1) to receive data latched by the data latching means (2). First and second P / S conversion means 3 and 4 for converting predetermined bytes into serial data, and framewords from the framer and control signal generating means 1 and the first and second P / S conversions. And a logical sum gate (5) for logically operating the respective data from the means (3,4). The apparatus of claim 1, wherein the frame word and control signal generating means (1) comprises: a distributing means (11) for generating a plurality of divided clocks which are divided at a predetermined rate by receiving a predetermined clock from the outside; Framer generation means 12 for generating a frame word at a predetermined period using the clock divided in 11), and the time slot is controlled to receive the clock divided by the division means 11 to receive the maintenance signal, respectively. And a control signal generating means (13) for generating signals (MEN, SEN) to retime and output the framewords from the frameword generating means (12) and the divided clocks. Signal framer. 3. The control signal generating means (13) according to claim 2, characterized in that the control signal generating means (13) is configured to retime the frameword from the frameword generating means (12) and the clocks of the main clocks at the falling edge of the predetermined clock provided from the outside. Signal framer of optical transmission system. 2. The apparatus of claim 1, wherein the first and second P / S converting means (3, 4) receive the control signals from the frame word and the control signal generating means (1) and are latched by the data latching means (2). A signal framer of an optical transmission system, characterized in that it is configured to convert data into serial data one byte each. 2. The data latching means (2) according to claim 1, wherein said data latching means (2) is an 8-bit parallel data (D [7: 0]), a write signal (WR *), and a first byte enable signal (M_ADIS). *), Receiving the second byte enable signal S_ADIS * and latching two bytes so that the first byte is the first P / S converting means 3 and the second byte is the second P / S converting means 4. And a signal framer of the optical transmission system. A frame word detection and control signal generating means 6 which receives a predetermined clock and maintenance data from the outside and detects a frame word to generate a predetermined control signal; and from the frame word detection and control signal generating means 6 S / P converting means (7) for receiving a specific control signal and S / P converting maintenance data from the outside, and receiving the control signal from the frameword detection and control signal generating means (6). First and second data latching means (8, 9) for latching 8-bit parallel data from the / P converter, and output signals are received by receiving predetermined input signals (HSEL *, LSEL *) from the outside. And output means (10) for selectively outputting data from said first and second data latching means. The method of claim 6, wherein the frame word detection and control signal generating means (6) detects a frame word (OxE8) in a predetermined frame input from the outside, and generates a control signal (DET) when a framer is detected. And a framer detecting means (61) and frequency division and control signal generating means (62) for generating a predetermined clock and control signal in accordance with the control signal (DET) from the framer detecting means (61). Signal relievers in the system. The frequency division and control signal generating means (62) receives the control signal (DET) from the framer detecting means (61) and generates a 64 kHz clock until it reaches 16 from the CP output terminal. The first terminal signal LDH maintains a logic '0' only between the 7th falling edge and the 8th falling edge of the clock outputted to the CP output terminal, and the 15th falling edge of the clock and the 16th falling edge. And outputting the second terminal signal (LDL) to maintain a logic '0' only between edges. The frame word detection and control signal generating means (6) receives a frame of the maintenance data bit and the 64 ms clock transmitted to the subscriber access device through the 155,520 Mb / s transmission system. OxE8) to detect and maintain frame synchronization to generate a predetermined control signal for the reframe. 7. The S / P conversion means (7) according to claim 6, wherein the S / P conversion means (7) receives a maintenance data bit string from the outside and performs serial-to-parallel conversion to a clock (CP) provided by the frameword detection and control signal generation means (6). To provide the converted parallel data to the first and second data latching means (8, 9).