JPS6238634A - Scramble processing system - Google Patents

Abstract

PURPOSE:To detect the information inserted to an additional bit before and after a self-synchronizing scramble circuit at the transmission side at the pre- stage or the post-stage of a self-synchronizing descramble circuit at the reception side by providing the self-synchronizing scramble circuit and the self- synchronizing descrambling circuit so as to apply scramble processing. CONSTITUTION:Information sets a, b... of each bit except insertion signals A, B... of an input data signal 101 are subject to scramble processing by a scramble signal 102 and becomes information sets a1, b1..., the insertion signals A, B... are sent to the output of an EX-OR circuit 1 as they are to obtain a data output signal 103. Thus, the insertion signals A, B are extracted before descramble processing at the reception side. A reception data signal 107 is branched and fed to a self-synchronizing descramble signal generating circuit 2a and an output data signal 111 equal to the input data signal 101 is obtained at the output of an EX-OR circuit 4. That is, when the insertion signal is a signal such as a supervisory data, the circuit is constituted to be extracted after descrambling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrambling process, and particularly to a self-synchronized scrambling process that can be used in digital wireless communication systems.

[Conventional technology]

In digital wireless communication systems, scramble processing is performed on transmission signals for the purpose of flattening the transmission spectrum in the radio section and making it easier to extract the clock signal on the receiving side. This scrambling process is performed in conjunction with the insertion/extraction (multiplexing) of parity conflict check bits, frame synchronization signals, and negotiation line signals (DSC signals) necessary for monitoring the wireless section, as well as the This is done by a signal processing device. In a digital wireless communication system such as a microwave band with a large transmission capacity, a digital multiplexed signal multiplexed by a digital multiplexing terminal device is input as an input signal. Scrambling processing is performed using a pseudo-random code (PN code).

For this reason, the signal processing equipment on the radio line side is designed to superimpose this and perform synchronous scrambling processing in synchronization with the frame synchronization signal, achieving the necessary spectrum flattening as a whole. It is configured to perform the reverse process (descrambling process) to restore the original digital multiplexed signal.

A method of scrambling is synchronous scrambling, in which the PN code output obtained from a PN code generator consisting of a shift register array with feedback coupling and the input data signal are added to an exclusive OR circuit to perform scrambling processing. A method using a circuit (sometimes called a reset type) and a desk simple circuit, and a completely blind self-synchronous type in which an exclusive OR circuit that performs scrambling is incorporated into the feedback loop of the PN code generator. Methods using scrambling circuits and descrambling circuits are known. The former prevents a bit error p occurring in the transmission path from spreading to other bits due to descrambling processing on the receiving side, and by controlling the PN code supplied to the exclusive OR circuit with a gate circuit, It is easy to stop the scrambling process of only the necessary time slots without affecting the bits of the time slot, and it is possible to insert and extract signals such as frame synchronization signals and DSC signals both before and after the scrambling process. It can be carried out. On the other hand, the latter method does not require external timing control, but a bit error of 91 bits that occurs in the transmission path may affect other bits due to desrambling processing on the receiving side. However, in the conventional circuit, scrambling processing is continuously performed on all time slots of the input data signal, so there is a drawback that signals cannot be freely inserted and extracted. Therefore, a synchronous scrambling and descrambling circuit is used in the scrambling processing method of a digital wireless communication system that inserts and extracts a frame synchronization signal and the like.

By the way, the radio receiving equipment of each intermediate relay station, including the receiving end station, constantly monitors the reception spectrum characteristics of each received signal, and when an abnormality is detected, it controls the adaptive equalization circuit provided in each receiving equipment. Compensation is performed so that the frequency spectrum of the receiver output becomes flat. The purpose of this compensation is to compensate for changes in transmission band characteristics (amplitude characteristics) due to fading or the like that occur in each radio transmission section, and to prevent deterioration of the bit error rate. In the conventional signal processing device of the transmitting terminal station, the scrambled digital multiplexed signal sent from the digital multiplexing terminal device is cut off, and the input of the signal processing device is “1” or “O”.
'', the transmission signal on the wireless line is only subjected to scrambling processing by the signal processing device, resulting in insufficient spectrum spreading and the compensation effect of the transmission band characteristics by the adaptive equalization circuit of each relay station wireless receiving device is reduced. In other words, in the case of a method such as a multiphase phase modulation method that transmits multiple digital multiplexed signals using one radio carrier wave, if one digital multiplexed signal is disconnected, the transmission quality of other digital multiplexed signals will be affected. This has the disadvantage that the number of code errors 9 increases.

As a method to solve this drawback, in addition to the above-mentioned synchronous scrambling process, each signal processing device is provided with a self-synchronizing scrambling means and an input signal disconnection detecting means to control this, and when the input signal is disconnected, the self-synchronizing scrambling means is provided. A signal processing device which activates a synchronous scrambling means and secures an effect equivalent to the scrambling processing using a necessary number of stages of PN codes in conjunction with the synchronous scrambling processing which is always in operation has been proposed by the applicant of the present patent application in the patent application Sho. It is proposed in the specification of No. 59-71317.

[Problems to be solved by the invention]

In order to realize a signal processing device for digital wireless communication using such self-synchronized scrambling means,
It is possible to configure a self-synchronized scrambling circuit and a self-synchronized descrambling circuit that can insert and extract parity check pits, frame synchronization signals, and DSC signals without affecting other bits. It becomes necessary.

An object of the present invention is to provide a self-synchronous scrambling circuit and a scrambling processing method using a self-synchronous descrambling circuit that can meet such demands. More specifically, a scrambling processing method that can detect before or after the self-synchronized descrambling circuit on the receiving side using information inserted into additional bits before or after the self-synchronized scrambling circuit on the sending side is proposed. It is to provide.

[Means for Solving the Problem] The scrambling processing method of the first invention is a scrambling processing method for digital communication in which the scrambling means on the transmitting side performs scrambling processing on an input data signal into which additional bits have been inserted by speed conversion. a self-synchronized scramble signal generation circuit that branches the output of the first exclusive OR circuit to generate a scramble signal, and an output of this self-synchronized scramble signal generation circuit. and a first gate circuit provided between the first exclusive OR circuit and the first gate circuit that is controlled by a first timing signal that specifies the time slot in which the additional bit is inserted, and The second descrambling means performs descrambling processing on the received data signal.
a self-synchronous descrambling signal generating circuit that has the same configuration as the self-synchronous scrambling signal generating circuit and generates a descrambling signal by branching the received data signal; A second timing signal provided between the output of the scramble signal generation circuit and the second exclusive OR circuit and controlled by a second timing signal generated on the receiving side in response to the first timing signal. and a gate circuit.

Further, in the scrambling processing method of the second invention, in the first invention, the scrambling means on the transmission side is further provided at the input of the self-synchronized scramble signal generation circuit, and the scrambling means is further provided at the input of the self-synchronized scramble signal generation circuit, and the scrambling means of the above-mentioned additional bits is configured to collect information after the scrambling process. a third gate circuit for inputting a predetermined code to the self-synchronized scramble signal generation circuit by a third timing signal specifying the time slot TF in which the signal is to be inserted; The predetermined code is input to the descramble signal generating circuit under the control of a fourth timing signal provided at the input of the descrambling signal generating circuit and generated on the receiving side in response to the third timing signal. It is configured by including a fourth gate circuit.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIGS. 1(al) and (b) are block diagrams of an embodiment of the first invention, and (a) shows a scramble circuit on the transmitting side,
(b) shows a desk simple circuit on the receiving side corresponding to this. The scrambling circuit f2) in FIG. 1 is a first exclusive OR circuit (EX-OR circuit) that performs scrambling processing on the input data signal 101 and the scramble signal 102.
1, a self-synchronized scramble signal generation circuit 2 that branches the output 103 of the EX-OR circuit 1 and generates the scramble signal 104, and between the output of the self-synchronized scramble signal generation circuit 2 and the EX-OR circuit 1. The self-synchronized scramble signal generating circuit 2 includes a NOR circuit 3 (first gate circuit) which is provided in the circuit and controlled by a first timing signal 105, and a self-synchronous scramble signal generating circuit 2 is controlled by a clock signal 105 as shown in the figure.
06, and an EX-OR circuit 22 that obtains the exclusive OR of the third and fourth stages. The descrambling circuit shown in FIG.
an OR circuit 4, a self-synchronous descrambling signal generating circuit 2a which has the same configuration as the self-synchronizing scrambling signal generating circuit 2 on the transmitting side and branches the received data signal 107 to generate a descrambling signal 109; The N0 gate circuit 5 (second gate circuit) is provided between the output of the synchronous descrambling signal generation circuit 2a and the EX-OR circuit 4 and is controlled by the second timing signal 110. The output data signal 111 is sent to the EX-OR circuit 4.
is output from. The two circuits described above have a configuration in which a NOR circuit 3 and a NOR circuit 5 are inserted into a known self-synchronous scrambling circuit and a descrambling circuit, respectively.

Next, the operation of the circuit shown in FIG. 1 (al and (b)) will be explained with reference to the timing chart shown in FIG.
In FIG. 1, the input data signal 101 input to the EX-OR circuit 1 is inserted into the time slot T of the additional pit as shown in FIG.

B... is the inserted data signal (lowercase letters represent data bits), and the timing signal 105 shown in FIG. There is. Due to this timing signal, among the information of each pit of the scramble signal 104 shown in FIG. 2 is added to the EX-OR circuit 1. Therefore, the information a, b, etc. of each pit except for the insertion signals A, B, etc. of the input data signal 101 are scrambled signals 10
2, the insertion signals A, B... are transmitted to the output of the EX-OR circuit 1 as they are without being changed, resulting in the data output shown in Figure 2. A signal 103 is obtained. In the conventional circuit, the output 104 of the self-synchronous scramble signal generation circuit 2 is directly applied to the EX-OR circuit 1, so that the time slot T of the insertion signal is also scrambled. For this reason, on the receiving side, the inserted signals A, B, and
... cannot be extracted without error. On the other hand, according to the circuit shown in FIG. 1(a), the inserted signals A, B... can be extracted before the entire descrambling process. Here, if the inserted signal is a frame synchronization signal, the frame synchronization signal inserted before the scrambling process can be extracted without being descrambled on the receiving side.

The descrambling circuit shown in FIG. 1(tb) uses the received data (g
No. 107 is a circuit for extracting inserted signals A, B, . . . without error after descrambling processing on the receiving side, and operates as follows. The received data signal 107 (Fig. 2 ■) is branched and applied to a self-synchronous descramble signal generation circuit 2a, and this self-synchronized descramble signal generation circuit 2a is a self-synchronized scramble signal generation circuit on the transmitting side. 2, the descrambled signal 109 that is its output is as shown in FIG. 2. The same timing signal 110 as shown in FIG.
7 is shown in Figure 2.9, the output of the EX-OR circuit 4 has an output data signal 111 (second
Figure I) is obtained.

That is, if the inserted signal is a signal such as monitoring data, it can be configured to be extracted after descrambling.

As explained above, according to the scrambling processing method using the circuit configurations shown in FIGS. 1(a) and 1(b), insertion signals A, B...
can be extracted without errors either before or after descrambling processing on the receiving side. Note that from the above explanation, it is clear that the inserted signal inserted into the additional focus at the edge of the scrambling circuit can also be extracted without error after descrambling.
The problem that occurs remains.

FIGS. 3(a) and 3(bl) are block diagrams of an embodiment of the second invention, in which insertion signals inserted before and after the scrambling circuit on the transmitting side are inserted before and after the descrambling circuit on the receiving side. This is a circuit that can extract any data bits without errors and without affecting other data bits.The difference between the scramble circuit in Figure 3 (al) and the scramble circuit in Figure 1 (a) is that A NOR circuit 6 (third gate circuit) controlled by the third timing signal 113 is provided on the input side of the synchronous scramble signal generation circuit 2, and the NOR circuit 7 (first gate circuit) receives the timing signal 113. and 114 are added.Also,
The descrambling circuit shown in FIG. 3 (bl) has a NOR circuit controlled by the fourth timing signal 120 on the input side of the self-synchronous descrambling signal generation circuit 2a, as in the case of the scrambling circuit shown in FIG. 3 (al). 8 (fifth gate circuit), and the NOR circuit 9 (second gate circuit) is configured to be controlled by timing signals 120 and 121. (This is a timing chart explaining the operation of the circuit bj. Among the time slots of additional bits inserted by speed conversion, the insertion signal A is inserted into the time slot Tl before the scrambling process.
, B... are inserted, and the inserted signal X is inserted into the time slot T2 after scrambling processing.

This shows the case where Y... is inserted. Figure 3(a)
The output data signal 112 of the scrambling circuit is as shown in FIG.
B... is being transmitted, but X is being transmitted in time slot T2.
, Y... are sent, and a, b... are sent to the other data bits. NO
Time slots T+ and T added to R circuit 7
A timing signal 113 (FIG. 4, ■, third timing signal) designating "t t".

114 (Fig. 4 ■), the scramble signal 115 (
(■) in Figure 4 becomes a scramble signal 116 (■) in Figure 4 and is applied to the EX-OR circuit 1, and each data bit except the additional bits is subjected to scrambling processing, but the information on the additional bits is transmitted as is and output. A data signal 117 (FIG. 4) is obtained. This output is branched and passes through a NOR circuit 6 to become an input signal 118 (FIG. 4). This input signal 118 is processed by a self-synchronous scramble signal generation circuit 2 to become a scramble signal 115. Of the output data signal 117, X in time slot T1 is then replaced with insertion signals X, Y... (for example, a DSC signal),
The signal shown in Figure 4 (■) is transmitted to the receiving side. Therefore, the additional bit insertion signals A, B... and X, Y... can all be extracted before being descrambled on the receiving side. , the received data signal 119 (Fig. 4 ■) is branched and inputted to the self-synchronized declarator/pull signal generation circuit 2a via the NOR circuit 8, but this input signal 122 is input to the transmitting side 9 as shown in Fig. 4 ■. Input signal 11 of self-synchronous scramble signal generation circuit 2 of
It will be the same as 8.

Therefore, the data bits excluding the time slots T, , T, are descrambled by the descrambling signal 123 (■ in Fig. 4), which is the reverse of the descrambling process of the scrambling circuit in Fig. 3 (al), and the output data signal 124 is The side data pins) a, b... are restored, and the time slot) T
t and Tt are insertion signals A and B of the received data signal.
and X, Y. are output. That is, the insertion signal X inserted after the scrambling process.

It is possible to take out Y... before or after the descrambling circuit without affecting other data bits. Therefore, a configuration is adopted in which a parity check virator is inserted and transmitted before the scrambling circuit on the transmitting side, and a parity check is performed by detecting this after descrambling on the receiving side.
Even if a signal is inserted, this will not cause false positives in the parity check.

In the above explanation, the input signals of the self-synchronized scramble signal generation circuit 2 and the descramble signal generation circuit 2a are set to ``0'' in time slot T2 using a NOR circuit. It may be configured to be '1'. Furthermore, although these circuits have been described as being used in combination with synchronous scrambling processing in the signal processing device proposed in Japanese Patent Application No. 59-71317, they can also be used independently, but It is not possible to eliminate the spread of bit errors that occur in other data bits.

〔Effect of the invention〕

As explained in detail above, according to the scrambling processing method of the present invention, information inserted into the additional bits before or after the scrambling processing is used before or after the descrambling processing on the receiving side by using the self-synchronized scrambling method. Or you can extract it later.

In particular, the scrambling method of the second invention has a feature that information inserted after scrambling does not affect other data bits.

Therefore, according to the present invention, the signal processing device proposed in Japanese Patent Application No. 59-71317 can be easily constructed.

[Brief explanation of drawings]

FIG. 1 (aJ and (b) is a block diagram showing an embodiment of the first invention, FIG. 2 is a timing chart explaining the operation of the circuit of FIG. 1 (aJ and (b), and FIG. 3 (aj and (b) is a block diagram showing an embodiment of the second invention;
The figure is a timing chart explaining the operation of the circuits in Figure 3 (al and (bl). 1.4.22... Exclusive OR circuit (EX-0
2... self-synchronous scramble signal generation circuit, 23... self-synchronous descramble signal generation circuit, 3, 5, 6, 7, 8.9... NOR circuit,
21...-shift register. Agent Patent Attorney Susumu Uchihara No1me I Kuniri (a-) Me 2nd 3rd session

Claims (2)

[Claims] (1) In a scrambling processing method for digital communication, the scrambling means on the transmitting side includes a first exclusive OR circuit that performs scrambling processing on an input data signal into which additional bits have been inserted by speed conversion; a self-synchronized scramble signal generation circuit that branches the output of the OR circuit to generate a scramble signal; and the additional circuit that is provided between the output of the self-synchronized scramble signal generation circuit and the first exclusive logic circuit; a first gate circuit controlled by a first timing signal specifying a time slot in which a bit is inserted; 2, a self-synchronous descrambling signal generating circuit that has the same configuration as the self-synchronous scrambling signal generating circuit and generates a descrambling signal by branching the received data, and this self-synchronous descrambling circuit. a second gate provided between the output of the signal generation circuit and the second exclusive OR circuit and controlled by a second timing signal generated on the receiving side in response to the first timing signal; A scrambling processing method characterized by comprising a circuit. (2) In a scrambling processing method for digital communication, the scrambling means on the transmitting side includes a first exclusive OR circuit that performs scrambling processing on an input data signal into which additional bits have been inserted by speed conversion; a self-synchronized scramble signal generation circuit that branches the output of the logical OR circuit to generate a scramble signal; and a self-synchronized scramble signal generation circuit that is provided between the output of the self-synchronized scramble signal generation circuit and the first exclusive OR circuit. A first gate circuit controlled by a first timing signal that specifies a time slot in which the additional bit is inserted, and a first gate circuit that is provided at the input of the self-synchronized scramble signal generation circuit to generate information after scrambling among the additional bits. a third gate circuit that inputs a predetermined code to the self-synchronized scramble signal generation circuit according to a third timing signal that specifies a time slot in which a signal is inserted; a second exclusive OR circuit in which the means performs descrambling processing on the received data signal;
a self-synchronous descrambling signal generating circuit having the same configuration as the self-synchronous scrambling signal generating circuit and branching the received data signal to generate a descrambling signal; an output of the self-synchronous descrambling signal generating circuit; a second gate circuit provided between the second exclusive OR circuit and controlled by a second timing signal generated on the receiving side in response to the first timing signal; and the descramble signal. The third
a fourth gate circuit that inputs the predetermined code to the self-synchronized descrambling signal generation circuit by a fourth timing signal generated on the receiving side in response to the timing signal of A scrambling processing method characterized by