IE41472B1 - Improvements in or relating to data processing equipment - Google Patents

Abstract

1448041 Data processor STANDARD TELEPHONES & CABLES Ltd 23 May 1974 23067/74 Heading G4A A data processor includes inputs connected to respective input staticizers, outputs connected to respective output staticizers, a random access memory arranged to store intermediate processing results, an input arranged to receive instructions having function and address parts, and a logic unit arranged to process one bit operands from the input staticizers and/or the random access memory to produce one bit results which are directed to an output staticizer or the random access memory, the operand source and result destinations being selected by the address parts of instructions whose function parts determine the operations to be performed, e.g. read, write, AND, OR. The processor may be used to interface controlled equipment, e.g. a telephone exchange, and a controlling digital computer and may be formed on a single integrated circuit chip. One or more of the processors may be supplied with instructions from an external read only program memory. Several such program memories storing respective programs may be provided, a selected one being supplied with clock pulses. In a first embodiment the input staticizers, output staticizers, and the random access memory are connected, together with a number of delay units formed by shift registers to internal input and output buses. All the units, input staticizer delays &c., together with various clock pulse sources are addressed by the address part of an instruction and the buses are connected to a push down stack. The processor performs AND and OR operations between the contents of the top two stack locations and loads the result into the top location. The result may also be transferred to any unit, e.g. output staticizer, addressed by the current instruction, or may be retained in the stack. In a second embodiment, Fig. 3, the random access memory RAM, delays DEL, and input and output staticizers IS, OS are connected to the logic unit via selectors WAS, RAS activated by the address part of an instruction ADO, the logic unit being controlled by the function part FO. The logic unit, Fig. 4, consists of two NAND gates N1, N2, each formed by an AND gate and a bi-stable, which NANDs successive operands. The instruction format allows the outputs of both NANDs to be connected to the input of the other NAND or to addressed units in the processor, output staticizers &c., and the Specification gives details of the way in which Boolean functions can be evaluated. Additional external random access memories may be coupled to the processor.

Description

This invention relates to data processing equipment, and especially to such equipment for use in the performance of relatively simple data processing operations.

The need for such processors exists in such systems as telephone exchanges where a digital computer ts used as the central controlling element of an exchange in which a multitude of electro-mechanical devices such as relays and either reed relays or cross-bar switches are to be used. Such processors can be used, inter alia, as an interface between the computer and the controlled equipments.

According to the invention there is provided an electrical data processor wherein the data to be processes consist of one-bit operands, wherein the inputs over which data bits for processing reach the processor are connected to respective ones of a set of input staticisers so that the received data bits are stored in respective ones of the staticisers, wherein output staticisers are provided which are arranged to selectively receive the one-bit numbers generated by the data processing operations, which output staticisers are connected to respective ones of a set of outputs via which the one-bit numbers generated by the operations are extractable from the processor, wherein a random access memory is provided for the storage of data, including intermediate processing results, for use in the data processing operations, wherein instructions words under whose control the processor operates each includes a function portion and an address portion, wherein a logic unit is provided which performs data processing operations on the one-bit operands under the control of the function portions of the instruction words, each said operation being performed on a single one-bit operand under the control of the function portion of one instruction word, wherein address selection means is provided to which the address portion of each said instruction word is applied, each said address portion being a single address, wherein the addresses one of which forms each said address portion include at least the addresses of the input and output staticisers and of the random access memory locations, wherein one-bit operands to be processed are each applied to the logic unit via a single data highway under the control of the address portion of a said instruction word, wherein the processing is effected one bit at a time under the control of the function portions of the instruction words, each one-bit operation occurring under the control of the function portion of a single one of said words, the result of each said operation being a single binary bit, i.e. 1 or 0, and wherein, dependent on the address portions of the instruction words the results of the data processing operations are selectively retained in the logic unit for use in a subsequent data processing operation, routed to one of the output staticisers defined by the instruction word's address portion, and routed to a random access memory location defined by an instruction word's address portions.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a first processor according to the invention.

Figure 2 is a shift-register delay element, usable in the processor of Figure 1, and also in that of Figure 3.

Figure 3 is a block diagram of a second processor according to the invention.

Figure 4 is a schematic of the logic unit of the processor of Figure 3. Figure 5 is a program generation circuit, usable with the processors of Figures 1 and 3. 41473 Big.6 shows how an external random access memory can be used with a processor according to the invention.

Bigs. 7 and 8 show how two processors according to the invention can he worked together.

The processors described herein, referred to as Boolean processors, are programmable logic devices each of whioh can replace a relatively slow-speed wired logic circuit. Such a device is a one bit processor for evaluating the Boolean equations forming a logic system specifica10 tion.

The first embodiment shown in Big.l has a set of input staticisers IS to which are applied the input conditions to he evaluated or processed. These can include such information as the condition, looped or unlooped, of a telephone line, and of that line's condition on a previous examination. In this example, a function needed could be to signal to the exchange's central processor if the line condition has changed. There is also a set of output staticisers OS, in which the results of processings are stored for sending to user equipments. These staticisers are connected to the single-wire internal busses BI and B2.

There is also a small internal random access memory RAM to meet the working memory needs of the proces25 sor, and in general one bit in this memory replaces one - 4 41472 bistable in a wired logic system. The processor's program is held in an external device such as a read-only memory which, if the program is a fixed cycle without branching, can be shared among a number of processors, which could apply in the line loop application. The number of processors controllable from one program memory depends on security considerations and on power drive capabilities.

The program memory supplies the instruction words sequentially via a set of inputs to a decoder DEC, which has address outputs and function outputs. The address outputs ADO go to read and write selection circuits (not shown) with access to the staticisers, the memory RAM, and such other elements as needed by the program. The function outputs EO go to an arithmetic logic unit ALU which does the actual processing. Associated with ALU is an operation stack ASO with four stages A-D: this is in effect a reversible shift register. These elements are all connected to the busses BI and B2; also connected to these busses are a set of delay elements DEL and a pulse divider RL.

The pulse divider receives clock pulses from the clock of the system which uses the processor, and it produces the clock pulses the processor needs by pulse division in known manner. The delay elements LED consist of one or more shift registers: when a bit has to be delayed - 5 41472 ?··· for a given period, this can he done by driving it along a shift register in DEI. The processor receives its·· power via inputs PI. Thus the device is a one-hit digital computer, hut without a program store, since the program words are applied to it via the inputs IP.

Within the processor, all inter-unit data flow is via the busses BI and B2,and the stack ASO.

The program is coded into eight hits, of which six specify an address location (input staticiser,· output staticiser, hit of RAM, delay element, clock), and two' ’. specify one of four functions. As mentioned above the program is cyclic, being stepped continually by an external* clock with the program steps presented to the processor's) one per step. The instruction set is: .15 (a) READ RD (h) READ & COMPLEMENT. . 55 (c) AND (WRITE) AND (c) OR (WRITE)» OR .

The functions RD and RD transfer data from the address location specified in the instruction to the top-, stage A of the stack ASO. As new data enters ASO, .its existing contents ripple downwards into successively ', lower portions, the data leaving D being lost.

AND and OR perform the Boolean operations AND and OR respectively on the contents of stages A and B of ASO, the results being written in an address specified in. the instruction, and also being placed in stage A. When -6,41472 this occurs the other stages move up once, I) being set to 0. .

The all zeroes address is used as a dummyaddress, i.e. it is not allocated to a physical location, being used for special purposes with all four instructions. Thus HD with the all zeroes address sets stage A of the stack ASO to 0,' while HE with the same address sets A to 1. The all zeroes address is used with AHD and OR when the result of the Boolean operation does not have to be placed in a particular location, merely remaining in A for use in a later Boolean operation.

In telephony one often needs to delay the operation and release of relays for timing and for differentiation between signals. This can be done by using clock15 driven shift registers, and the block DEL contains five such shift registers to which may be connected any one of seven internal clocks of different frequencies, obtained from the pulse divider RD. The input, output, and clock of such a register are each addressable as one address location. The clocks used and the lengths of the shift registers provide delays ranging from 25 ms to 5 seconds, and the accuracy of the timing depends on the number of stages in the registers.

Big,2 shows one example of a delay element usable in the block DEL, Big.l, and also usable in the processor - 7 41473 of Fig.5, to be described later. It is a so-called inertial delay element, and it delays the leading edge, but not the trailing edge of a pulse. It consists of a clocked bistable which drives a clocked shift register.

If the time for which the signal input is high is less than the delay introduced by the register then no output is obtained from it. To delay tbe trailing edge only, the same circuit is used, but in this case the input signal is Inverted before it reaches tbe delay element, and one takes the inverse of the output from the shift register.

In some cases it is not convenient to implement a delay by shift register: in this case the effect can be achieved in software manner by programming.

The total addressing field, with 6 bits available, has 64 locations, as follows (assuming that the processor is used in a centrally controlled telephone exchange). (a) locations 1-10 Standard signals sent or received between tbe processor and central control, some of which are write only, one of the staticisers OS being cleared when its content is sent out, and some of which are read only, for signals to I.S., one of the staticisers IS being cleared when its content is read, (b) locations 11-18 Inputs and outputs from and to the associated, peripheral circuit hardware (e.g. relays), inputs being read only and outputs write only. (c) Locations 19-25 Belay elements. (d) Locations 24-50 The built-in clocks (from ED). (e) Locations 31-63 These are the bits of HAM, used as working storage when processing. (f) Location 0 With function EB this sets stage A of ASO to 0 and with HD it sets A to 1. It is also used as a dummy address (see above) with functions AND and OR.

The program is so devised that the processor can be used to replace a number of relays in a switching circuit. Thus it can do such functions as compare the current state of a line loop or a relay with its state, say, 100 ms. ago, or produce an output when certain specified sets of conditions exist. Some of these functions need a large number of program steps (e.g. 250), but the time taken to produce a result is compatible with the operating times of electromagnetic components. Thus in many cases, such processors are a convenient interface between a digital computer and various elements of a telephone exchange. The blocks in Fig. 1 can each follow conventional practice, and such a processor is preferably made as a single-chip integrated circuit, e.g. using MOS techniques. It could, if desired, be implemented using discrete components, but this would - 9 41472 lose many of the benefits obtainable from small size.

We now turn to the second - and at the time of writing preferred - embodiment of the invention, Figs. 3-6. This differs in a number of respects from the processor of Fig.l, but where possible the same references are used for the same circuit elements. This processor, when made as a single-chip integrated circuit unit, has some resemblance to a 64- bit read-write random access memory unit. Much Of the circuitry shown is decoding logic used to address data stored in the processor. The six-bit addresses are applied directly via inputs ADO to the decoders, in this case the write address selector WAS and the read address selector RAS, and for a whole program step the input and output data highways IH and OH for the logic unit ALU are connected to the appropriate storage bit. Note that, as in Fig.l, the staticiseis IS and OS, the delay elements DEL and tbe clock LFC are treated as address locations. A write pulse is generated within ALU when data is clocked therefrom into an address loca20 tion, which pulse is sent from AIU over the highway WH.

Inputs to the processor come via noise filter inertial delay circuits NF, which delay the input transitions, so that spurious signals are not seen by the processor, and from NF the input data reach the input staticisers IS. At the start of each program cycle, the information at the outputs of NE is latched into the staticisers IS under control of a clock signal generated when a particular program word is used, which word is put at the beginning of each program. The outputs of IS are connec5 ted into the address selector RAS, which provides the inputs to the logic unit ALU via the highway IH, and are treated as address locations, like the outputs from the bit cells of RAM. As seen by the logic unit ALU, they are read-only storage. Similarly the output staticisers OS are connected to WAS, and appear to ALU as write-only storage whose outputs are accessible to the outside world.

The delay units in the block DEL (see Eig.2) each have three addressable points, the input, output and clock input. The first two are treated in the same way as one bit of RAM, although the output is from the end of a shift register. The input to the clock LEO is a write-only location, like OS, and the read-only locations with the same addresses contain a range of low frequency clocks usable as the delay unit clocks. These clocks are only high for one program cycle, and so must be reset by the clock used for IS.

The heart of the processor is the unit ALU, which performs the Boolean operations on the stored data. This, Eig.4, is based on two-level NAND units NI and N2, each including an AND gate and a latch. When a clock pulse is applied to the latch of such a HAND unit via its connection such as EP, its contents are up-dated so that they become the AHDing of the previous data in the unit and of an input thereto. The output of such a HAND unit is the inverse of the data In the bistable.

The unit ALIT also includes control circuitry ED which decodes the function bits of a program word (received via BO) and also detects an all zeroes address, and some gates to route signals from one HAND unit to the other.

When the function bits of an instruction are SD, the input of HAND unit Hl is connected via the Input Selection Logic (part of RAS) to the output line from the storage units in the rest of the processor. In addition, a clock pulse is generated for Hl, whose latch was previously set to 1 on the last HAND instruction. Burther RD instructions are similarly treated and the AHD total is built up on the bistable of Hl. Note that the four functions used in the processor of Bigs. 5-6 are not quite the same as those of that of Big. 1. Here they are: (a) RD - read data into the first HAND unit Hl (b) RD - read the complement of this data into the .first HAND unit N1 (c) HD - transfer data from Hl to H2 if address is zero, or for any other address write data thereto (d) WR - write the data in N2 back to the input of Hl if the address is zero, or for any other address write data thereto.

When a NANI instruction is decoded, the control I'D checks that the address is zero, and the output selec5 tion logic 01 switches the output of Nl to the input of N2, and generates a clock pulse for the latch of N2, which was previously set to 1. If the address is other than zero, FD switches the output of Nl to the output data highway OH (Fig. 5), and also generates a write pulse sent out over lead WH. Another series of Hl (or Hl) instructions should now be decoded, and Nl fills up with the NANling of the data held in the associated addresses, since the NANI instruction cleared the previous total in Nl. Another NANI 0 instruction causes the control FI to clock the latch of N2, and to fill it with its previous contents AN1 the output of Nl. A write instruction V/H presents the output of N2 to the output data highway OH and generates a write pulse (sent over TO) unless the associated address is 0, in which case this data is fed back into Nl as new input data. In this respect the operation resembles that of the processor of Fig. 1.

Other latches or bistables in the control FI allow it to remember previous instructions, so that shorter------1------------------------------------------ 15 41473 programs can be used. Thus there is no need to have HAND 0, WRITE X (RE-O, WR-X) since if WR-X immediately follows a read instruction both are executed. Similarly, if a WR instruction is decoded the output is held in a latch, so that if another WR instruction follows the same data can be sent out. In the absence of this facility, the whole processing operation would have to be performed again if the result has to be written in more than one location.

The logic unit ALU can be based on AND/OR, OR/AND, NOR/NOR or EAND/NAND, all of which are equivalent in terms of the number of instructions needed for a given equation. The latter two are more flexible as they allow a result to be complemented (if necessary) by one additional instruction, whereas with the former two, two additional instructions are needed. NAND/NAND is preferred as it is compatible with the normal form sum of products used to write Boolean equations.

The logic unit A1U sometimes has to do two operations in one program step, as well as clearing data in one of the latches), so three phases of clock are needed in each program step. > Thus the processor's main clock must be t three times the frequency of the clock which drives the f program counter.

Now the program generation circuit, Fig. 5, which - 14 41472 is associated with, hut not part of the processor, will he described. The program words themselves are held in a standard read-only memory ROM, e.g. of 256 eight-bit words, which as indicated, can serve a number of similar Boolean processors such as BP1 and BP2. The number servable is limited by drive limitations and security considerations. Each of the words in ROM is addressed in turn by a program counter PC. As programs may be of different lengths, tbe counter PC is reset by the last word in the program, and the all ones instruction word WR63 is used for this because it is easily detected. This word activates an 8-input AND gate G1 which resets PC via the connection R when the last word of a program is read out.

A clock is needed to drive the counter PC and tbe processors, and this clock can either be fed to several programs (in different stores such as ROM) or generated locally at each counter PC. This second method is used as it enhances system security and reduces interconnections between units. A highly stable and accurate clock is not needed as it is only used within the Boolean processor system and is not related to any of a processor's inputs and outputs. Hence a simple RC oscillator OSC can be used. The counter, reset circuit and oscillator, whioh are shoWn inside a dotted box, oould be on a single LSI chip. They may even be combined on the same chip - 15 41472 with ROM, to give a chip with no more than 16 pins, which would be the only component external to the processor needed to make it work.

Several possible LSI techniques can be used to make Boolean processors such as described herein: no technology is ruled out because of speed restrictions.

With metal gate MOS the chip is about 140 X 140 mils, which is a medium sized chip. Slightly less area is needed for collector diffusion isolation (CDI), in which case it may be possible to have relay drivers on the chip due to the high current capabilities of OD'I. Also the circuits could, if needed, be run at higher speeds than for the MOS case.

The Boolean processor program consists in essence of a list of system definition equations evaluated sequentially, one at a time, in a fixed cycle. Bor correct operation the inputs must not change during a program cycle, hence the staticisers IS, so the first step in the cycle is to clock these staticisers. To do this, a single address is allocated to these clocks, and the address decode output therefor is connected directly to the clock line so that only the address part of the program word is effective when accompanied by either the ND or WR instruction. Thus the same address can be used with either of the read instructions (RD or RD) to read an - 16 41472 internally derived clock such as LFC The following indicate a few typical Boolean' equations, with the codings used.

X = A.B.C.D.E. X = A+B+G+S+B RD A RD A RD B RD B RD C RD C RD D RD D RD E RD E TO X ND X Note that the only difference is that when ANDing the last instruction is TO, whereas when ORing it is ND. X = (ABC+DE)EG + JKIi E (1) RD A (8) RD (2) RD B (9) RD G (3) RD 0 (10) ND 0 (4) ND 0 (ID RL J (5) RL L (12) RD K (6) RL E (13) RD I (7) TO 0 (14) TO X Eor equations with only AND or OR functions, i.e. single level, the number of steps equals the number of variables. Where there are two or more logic levels (e.g. AND and OR), the number of s teps is the number of variables, plus the number of 05 operations, plus the number of brackets used.

One can often reduce the number of steps byusing additional bits of RAM. For example, the·equation X = A+B+C+D+E + J.K.L.II as it stands needs 10+5 = 15 steps, but if it is re-written as two equations: Y = A+B+C+D+E X = Y + J.K.L.M. we have 6 steps for the first equation and 7 for the second one. This needs one bit of RAM to store the interim result Y. This technique is valuable where enough RAM bits exist.

The RAM bits are used in two ways, (a) to store status-defining variables and (b) to store partial results.

The first is fundamental to sequential switching circuit operation, and needs the status-defining variable to be permanently assigned to a particular RAM bit throughout the program cycle. The second use is not essential, but can be useful, as indicated above. A particular bit of RAM can store different partial results at different points in the program cycle.

The processing power of the Boolean processor is related to the size of its RAM, which is limited by the available addressing range. However, the effective memory size can be increased by tbe use of a so-called 41478 one-bit FIFO; thia is a first in, first out store with a number of memory elements but only one input port and one output port. Data written in by successive write instructions is read out in the same order by successive read instructions, and the FIFO can be addressed as if it were a single bit of RAM. Such a memory, which is functionally a delay-line store, is particularly suited to the storage of variables associated with the software realisation of shift registers, delay elements and ripple-through counters.

If the processor's data line is brought out to an external connection, additional RAM can be introduced as shown in Fig.6 where an external 64 bit RAM is added to the processor BP1. The programs word is extended to 9 bits to allow for the doubled address range now needed. Change15 over from internal to external addressing is by the external RAM enable input ERA to 3P1. Naturally further increase in the program word length allows more external RAM to be addressed.

Another way to make additional inputs, outputs and delay elements available is to use two (or more) Boolean processors in combination. For this, one must be disabled while tbe other is working and some means of switching from one processor to the other is needed, see Figs.7 and 8. Fig.7 uses spare outputs on each processor to control program changeover, while Fig.8 uses spare inputs.

Both methods can be made available to permit flexibility in use.

Claims (10)

1. An electrical data processor wherein the data to be processed consist of one-bit operands, wherein inputs over which data bits for processing reach the processor are connected to respective ones of a set of input staticisers so that the received data bits are stored in respective ones of the staticisers, wherein output staticisers are provided which are arranged to selectively receive the one-bit numbers generated by the data processing operations, which output staticisers are connected to respective ones of a set of outputs via which the one-bit numbers generated by the operations are extractable from the processors, wherein a random access memory is provided for the storage of data, including intermediate processing results, for use in the data processing operations, wherein instruction words under whose control the processor operates each include a function portion and an address portion, wherein a logic unit is provided which performs data processing operations on the one-bit operands under the control of the function portions of the instruction words, each said operation being performed on a single one-bit operand under the control of the function portion of one instruction word, wherein address selection means is provided to which the address portion of each said instruction word is applied, each said address portion being a single address, wherein the addresses one of which forms each said address portion include at least the addresses of the input and output staticisers and of the random access memory locations, wherein one-bit operands to be processed are each applied to the logic unit via a single data highway uhder the control of the address portion of a said instruction word, wherein the processing is effected one bit at a time under the control of the function portions of the instruction words, each one-bit operation occurring under the control of the function portion of a single one of said words, the result of each said operations being a single binary bit, i.e. 1 or 0, and wherein, dependent on the address portions of the instruction words the results of the data processing operations are selectively retained in the logic unit for use in a subsequent data processing operation, routed to one of the output staticisers defined by an instruction word's address portion, and routed to a random access memory location defined by an instruction word's address portion.

2. A processor as claimed in claim 1, and wherein the logic unit includes a stack of individual storage sections together forming a reversible shift register, AND circuit means to perform an AND operation on data in two of said sections and to place the result thereof in one of said sections, and OR circuit means to perform an OR operation on the data in said two sections and to place the result thereof in said one section, the choice between OR and AND being determined by the function portion of the current instruction word.

3. A processor as claimed in claim 2, wherein when a said OR or AND operation'is performed and the address portion of the current instruction word defines an output staticiser or a random access memory location the result of the operation is sent to the address as well as being maintained in said one of the sections, and wherein when an OR or AND operation is executed and the address of the instruction word is a zero address the result is retained in one section and is not sent to any other part of the equipment.

4. A processor as claimed in claim 1, and wherein said logic unit includes two cascaded NAND circuits which perform the data processing operations.

5. A processor as claimed in claim 4, wherein the first of said NAND circuits receives data from the random access memory or the input staticisers under control of the address portion while either of the NAND circuits can supply results to the random access memory or the output staticisers under control of the address portion, wherein each said NAND circuit has an output selectively connectable under the control of a control circuit to the other of said NAND circuits, and wherein said control circuit is controlled by the instruction words.

6. A processor as claimed in claim 5, and wherein each said NAND circuit includes a two-input AND gate with its output connectable, under control of the control circuit, to the 1 side of a latch, a connection from the 1 side of the latch to one input of the gate, an input connection to the other input of the gate, and an output from the 0 side of the latch.

7. A processor as claimed in any one of the preceding claims, and which includes delay elements each arranged to delay a data bit by a preset increment of time, and clock means to generate clock pulses at a plurality of bit rates.

8. A processor as claimed in any one of the preceding claims, and which is formed as a single chip integrated circuit unit. 5

9. A data processing system which includes the combination of one or more data processors each of which is as claimed in any one of claims 1 to 8, the said instruction words the or each said processor 10. Each said processor.

10. Data processing eq with reference to Figures the accompanying drawings. and a program memory from which for controlling the operations of are applied one at a time to the or ipment substantially as described and 2, or Figures 3 and 4 of Dated this 23rd day of Hay 1975,