HU183139B - Electronic decoding circuit arrangement for systems with self-synchronization - Google Patents

Electronic decoding circuit arrangement for systems with self-synchronization Download PDF

Info

Publication number
HU183139B
HU183139B HU118980A HU118980A HU183139B HU 183139 B HU183139 B HU 183139B HU 118980 A HU118980 A HU 118980A HU 118980 A HU118980 A HU 118980A HU 183139 B HU183139 B HU 183139B
Authority
HU
Hungary
Prior art keywords
input
pulse
circuit arrangement
pulse generator
comparator
Prior art date
Application number
HU118980A
Other languages
English (en)
Hungarian (hu)
Inventor
Jozsef Mara
Geza Molnar
Karoly Molnar
Original Assignee
Magyar Optikai Muevek
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magyar Optikai Muevek filed Critical Magyar Optikai Muevek
Priority to HU118980A priority Critical patent/HU183139B/hu
Priority to FR8109408A priority patent/FR2482802A1/fr
Publication of HU183139B publication Critical patent/HU183139B/hu

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
HU118980A 1980-05-14 1980-05-14 Electronic decoding circuit arrangement for systems with self-synchronization HU183139B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
HU118980A HU183139B (en) 1980-05-14 1980-05-14 Electronic decoding circuit arrangement for systems with self-synchronization
FR8109408A FR2482802A1 (fr) 1980-05-14 1981-05-12 Dispositif electronique de decodage d'informations pour un dispositif fonctionnant en auto-synchronisation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
HU118980A HU183139B (en) 1980-05-14 1980-05-14 Electronic decoding circuit arrangement for systems with self-synchronization

Publications (1)

Publication Number Publication Date
HU183139B true HU183139B (en) 1984-04-28

Family

ID=10953254

Family Applications (1)

Application Number Title Priority Date Filing Date
HU118980A HU183139B (en) 1980-05-14 1980-05-14 Electronic decoding circuit arrangement for systems with self-synchronization

Country Status (2)

Country Link
FR (1) FR2482802A1 (enExample)
HU (1) HU183139B (enExample)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3510786A (en) * 1967-07-17 1970-05-05 Ibm Synchronizing circuit compensating for data bit shift
US3631422A (en) * 1969-02-03 1971-12-28 Ibm System for detection of data time interval measurement
DE2460534B2 (de) * 1974-12-20 1977-12-01 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur decodierung von von magnetschichtspeichern gelieferten lesesignalen
DD124408A3 (enExample) * 1975-04-09 1977-02-23
DE2804593C2 (de) * 1978-02-03 1979-09-27 Institut Fuer Rundfunktechnik Gmbh, 8000 Muenchen Verfahren und Anordnung zum Demodulieren eines binär codierten, phasenmodulierten Signals
DE2905668A1 (de) * 1978-06-15 1979-12-20 Rca Corp Anordnung fuer das magnetische aufzeichnen eines binaercodierten signals

Also Published As

Publication number Publication date
FR2482802A1 (fr) 1981-11-20
FR2482802B1 (enExample) 1984-06-08

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Legal Events

Date Code Title Description
HU90 Patent valid on 900628
HMM4 Cancellation of final prot. due to non-payment of fee