HK1152807A1 - Integrated circuit with multiported memory supercell and data path switching circuitry - Google Patents

Integrated circuit with multiported memory supercell and data path switching circuitry

Info

Publication number
HK1152807A1
HK1152807A1 HK11106840.6A HK11106840A HK1152807A1 HK 1152807 A1 HK1152807 A1 HK 1152807A1 HK 11106840 A HK11106840 A HK 11106840A HK 1152807 A1 HK1152807 A1 HK 1152807A1
Authority
HK
Hong Kong
Prior art keywords
integrated circuit
data path
path switching
switching circuitry
memory supercell
Prior art date
Application number
HK11106840.6A
Other languages
English (en)
Chinese (zh)
Inventor
‧希尤
‧莉莉
Original Assignee
蘋果公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 蘋果公司 filed Critical 蘋果公司
Publication of HK1152807A1 publication Critical patent/HK1152807A1/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
HK11106840.6A 2009-02-13 2011-07-05 Integrated circuit with multiported memory supercell and data path switching circuitry HK1152807A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/371,363 US8036061B2 (en) 2009-02-13 2009-02-13 Integrated circuit with multiported memory supercell and data path switching circuitry
PCT/US2010/024021 WO2010093868A1 (en) 2009-02-13 2010-02-12 Integrated circuit with multiported memory supercell and data path switching circuitry

Publications (1)

Publication Number Publication Date
HK1152807A1 true HK1152807A1 (en) 2012-03-09

Family

ID=42559800

Family Applications (1)

Application Number Title Priority Date Filing Date
HK11106840.6A HK1152807A1 (en) 2009-02-13 2011-07-05 Integrated circuit with multiported memory supercell and data path switching circuitry

Country Status (9)

Country Link
US (1) US8036061B2 (ko)
EP (1) EP2396886A4 (ko)
JP (1) JP5162024B2 (ko)
KR (1) KR101183739B1 (ko)
CN (1) CN101971498B (ko)
BR (1) BRPI1008499B1 (ko)
HK (1) HK1152807A1 (ko)
RU (1) RU2481652C1 (ko)
WO (1) WO2010093868A1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9563556B2 (en) * 2010-11-04 2017-02-07 Rambus Inc. Techniques for storing data and tags in different memory arrays
US9514069B1 (en) * 2012-05-24 2016-12-06 Schwegman, Lundberg & Woessner, P.A. Enhanced computer processor and memory management architecture
TWI550403B (zh) * 2013-04-02 2016-09-21 晨星半導體股份有限公司 記憶體控制器及其記憶體位址產生方法
KR101533685B1 (ko) 2013-11-29 2015-07-03 숭실대학교산학협력단 다중 프로세서용 메모리 장치 및 이를 포함하는 메모리 시스템
US10949546B2 (en) * 2017-08-02 2021-03-16 Samsung Electronics Co., Ltd. Security devices, electronic devices and methods of operating electronic devices
US11921637B2 (en) * 2019-05-24 2024-03-05 Texas Instruments Incorporated Write streaming with cache write acknowledgment in a processor
KR20210122461A (ko) * 2020-04-01 2021-10-12 에스케이하이닉스 주식회사 메모리 시스템의 입출력 성능을 향상시키는 장치 및 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06202949A (ja) * 1993-01-06 1994-07-22 Yokogawa Electric Corp マルチプロセッサ・キャッシュ制御装置
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
ATE376255T1 (de) * 1998-08-18 2007-11-15 Infineon Technologies Ag Halbleiterchip mit oberflächenabdeckung
US6108233A (en) * 1999-08-27 2000-08-22 Lucent Technologies Inc. Ultra low voltage static RAM memory cell
GB2373595B (en) * 2001-03-15 2005-09-07 Italtel Spa A system of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
US6789155B2 (en) * 2001-08-29 2004-09-07 Micron Technology, Inc. System and method for controlling multi-bank embedded DRAM
US6769050B1 (en) * 2001-09-10 2004-07-27 Rambus Inc. Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
US6621752B2 (en) * 2001-10-03 2003-09-16 Infineon Technologies Aktiengesellschaft Refreshing scheme for memory cells a memory array to increase performance of integrated circuits
DE10245037B4 (de) * 2002-09-26 2007-08-23 Infineon Technologies Ag Verfahren zum Entwurf von DRAM-Halbleiter-Speicherbauelementen
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
JP2004355271A (ja) * 2003-05-28 2004-12-16 Toshiba Corp データ転送システム
JP4336848B2 (ja) * 2004-11-10 2009-09-30 日本電気株式会社 マルチポートキャッシュメモリ及びマルチポートキャッシュメモリのアクセス制御方式
JP4989872B2 (ja) * 2005-10-13 2012-08-01 ルネサスエレクトロニクス株式会社 半導体記憶装置および演算処理装置
KR100655081B1 (ko) * 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
US7600081B2 (en) * 2006-01-18 2009-10-06 Marvell World Trade Ltd. Processor architecture having multi-ported memory
US7817470B2 (en) * 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture

Also Published As

Publication number Publication date
US8036061B2 (en) 2011-10-11
US20100208540A1 (en) 2010-08-19
RU2011137523A (ru) 2013-04-10
JP2011517219A (ja) 2011-05-26
CN101971498B (zh) 2014-05-07
BRPI1008499A2 (pt) 2016-03-08
BRPI1008499B1 (pt) 2020-10-06
WO2010093868A1 (en) 2010-08-19
CN101971498A (zh) 2011-02-09
KR20100127317A (ko) 2010-12-03
KR101183739B1 (ko) 2012-09-17
JP5162024B2 (ja) 2013-03-13
EP2396886A4 (en) 2015-09-02
RU2481652C1 (ru) 2013-05-10
EP2396886A1 (en) 2011-12-21

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20220217