HK1118378A1 - Semiconductor package structure having multiple heat dissipation paths and method of manufacture - Google Patents

Semiconductor package structure having multiple heat dissipation paths and method of manufacture

Info

Publication number
HK1118378A1
HK1118378A1 HK08109303.5A HK08109303A HK1118378A1 HK 1118378 A1 HK1118378 A1 HK 1118378A1 HK 08109303 A HK08109303 A HK 08109303A HK 1118378 A1 HK1118378 A1 HK 1118378A1
Authority
HK
Hong Kong
Prior art keywords
manufacture
heat dissipation
semiconductor package
package structure
multiple heat
Prior art date
Application number
HK08109303.5A
Other languages
English (en)
Inventor
Stephen St Germain
Phillip Celaya
Roger Arbuthnot
Francis J Carney
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Publication of HK1118378A1 publication Critical patent/HK1118378A1/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
HK08109303.5A 2006-08-30 2008-08-20 Semiconductor package structure having multiple heat dissipation paths and method of manufacture HK1118378A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/468,542 US7495323B2 (en) 2006-08-30 2006-08-30 Semiconductor package structure having multiple heat dissipation paths and method of manufacture

Publications (1)

Publication Number Publication Date
HK1118378A1 true HK1118378A1 (en) 2009-02-06

Family

ID=39150346

Family Applications (1)

Application Number Title Priority Date Filing Date
HK08109303.5A HK1118378A1 (en) 2006-08-30 2008-08-20 Semiconductor package structure having multiple heat dissipation paths and method of manufacture

Country Status (3)

Country Link
US (1) US7495323B2 (zh)
CN (1) CN101136380B (zh)
HK (1) HK1118378A1 (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7622796B2 (en) * 2005-09-13 2009-11-24 Alpha And Omega Semiconductor Limited Semiconductor package having a bridged plate interconnection
US7683464B2 (en) * 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
DE102007007159B4 (de) * 2007-02-09 2009-09-03 Technische Universität Darmstadt Gunn-Diode
US8035221B2 (en) * 2007-11-08 2011-10-11 Intersil Americas, Inc. Clip mount for integrated circuit leadframes
US8680658B2 (en) * 2008-05-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Conductive clip for semiconductor device package
US8086302B2 (en) * 2008-06-30 2011-12-27 Medtronic, Inc. Cardiac signal sensor control based on perfusion sensing
US7759778B2 (en) * 2008-09-15 2010-07-20 Delphi Technologies, Inc. Leaded semiconductor power module with direct bonding and double sided cooling
US8664038B2 (en) * 2008-12-04 2014-03-04 Stats Chippac Ltd. Integrated circuit packaging system with stacked paddle and method of manufacture thereof
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
US8354303B2 (en) * 2009-09-29 2013-01-15 Texas Instruments Incorporated Thermally enhanced low parasitic power semiconductor package
US9391005B2 (en) * 2009-10-27 2016-07-12 Alpha And Omega Semiconductor Incorporated Method for packaging a power device with bottom source electrode
US8421210B2 (en) * 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8436429B2 (en) * 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method
US9070721B2 (en) * 2013-03-15 2015-06-30 Semiconductor Components Industries, Llc Semiconductor devices and methods of making the same
US20150060123A1 (en) * 2013-09-04 2015-03-05 Texas Instruments Incorporated Locking dual leadframe for flip chip on leadframe packages
KR20150035253A (ko) * 2013-09-27 2015-04-06 삼성전기주식회사 전력 반도체 패키지
US9508625B2 (en) * 2014-04-01 2016-11-29 Infineon Technologies Ag Semiconductor die package with multiple mounting configurations
US9379193B2 (en) * 2014-08-07 2016-06-28 Semiconductor Components Industries, Llc Semiconductor package for a lateral device and related methods
DE102014118628A1 (de) * 2014-12-15 2016-06-16 Infineon Technologies Ag Bondingschlip, Träger und Verfahren zum Herstellen eines Bondingclips
CN106449536A (zh) * 2016-03-25 2017-02-22 苏州固锝电子股份有限公司 抗浪涌型表面贴装半导体器件
US9806008B1 (en) * 2016-06-14 2017-10-31 Infineon Technologies Americas Corp. Clip based semiconductor package for increasing exposed leads
US9941193B1 (en) * 2016-09-30 2018-04-10 Infineon Technologies Americas Corp. Semiconductor device package having solder-mounted conductive clip on leadframe
EP3693992A1 (en) * 2019-02-11 2020-08-12 Nexperia B.V. Surface mount semiconductor device and method of manufacture
JP7286450B2 (ja) * 2019-07-10 2023-06-05 新光電気工業株式会社 電子装置及び電子装置の製造方法
JP7271381B2 (ja) * 2019-09-20 2023-05-11 株式会社東芝 半導体装置
EP3882969B1 (en) 2020-03-18 2024-05-01 Nexperia B.V. A cascode semiconductor device and method of manufacture
DE102020109703A1 (de) 2020-04-07 2021-10-07 Infineon Technologies Ag Halbleitergehäuse und verfahren zu seiner herstellung

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6630726B1 (en) * 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
US7394150B2 (en) * 2004-11-23 2008-07-01 Siliconix Incorporated Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
US7504733B2 (en) * 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package

Also Published As

Publication number Publication date
US7495323B2 (en) 2009-02-24
US20080054438A1 (en) 2008-03-06
CN101136380B (zh) 2011-02-16
CN101136380A (zh) 2008-03-05

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20210822