HK1069007B

HK1069007B - Overlapping conderser

Info

Publication number: HK1069007B
Application number: HK05101302.6A
Authority: HK
Inventors: 富樫正明; 今井一郎
Original assignee: Tdk株式会社
Priority date: 2003-03-12
Filing date: 2005-02-16
Publication date: 2009-04-24

Description

Laminated capacitor

Technical Field

The present invention relates to a multilayer capacitor having a significantly reduced equivalent series inductance (ESL), and more particularly to a multilayer ceramic capacitor capable of reducing a voltage variation of a power supply for a CPU.

Background

In recent years, with the increase in processing speed and high integration, the operating frequency of a CPU (main processing unit) that can be used in an information processing apparatus has increased, and the current consumption has significantly increased. Further, therefore, the operating voltage tends to decrease due to the decrease in power consumption. Therefore, it is very difficult for a power supply for supplying power to a CPU to generate a larger current change at a high speed and to suppress a voltage change accompanying the current change within an allowable value of the power supply.

Therefore, as shown in fig. 7, a multilayer capacitor 100 called a decoupling capacitor is connected to a power supply 102 and is frequently used for the purpose of stabilizing the power supply. When the current changes transiently at a high speed, the current is supplied from the multilayer capacitor to the CPU104 by rapid charge and discharge, so that the voltage change of the power supply 102 is suppressed.

However, with the recent increase in the operating frequency of CPUs, the current change has become faster and larger. Therefore, the equivalent series inductance (ESL) of the multilayer capacitor 100 shown in fig. 7 is relatively large. As a result, the equivalent series inductance has a large influence on the voltage variation of the power supply.

That is, in the conventional multilayer capacitor 100 used in the power supply circuit of the CPU104 shown in fig. 7, ESL as a parasitic component shown in the equivalent circuit of fig. 7 is large. Therefore, as shown in fig. 8, the ESL inhibits charging and discharging of the multilayer capacitor 100 with a change in the current I. Therefore, as described above, the change in the power supply voltage V is likely to increase as shown in fig. 8, and cannot be applied to the future high-speed CPU.

This is because the voltage change during charging and discharging, which is a transient current, is approximated by the following equation 1, and the level of ESL is related to the magnitude of the power supply voltage change.

dV-ESL di/dt … formula 1

In the formula, dV is a voltage change (V) at the time of transient, i is a current (a) at the time of change, and t is a change time (sec).

Meanwhile, the external appearance of the conventional capacitor is shown in fig. 9, and the internal structure thereof is shown in fig. 10, and a conventional multilayer capacitor 100 will be described below based on these drawings. That is, in order to obtain the electrostatic capacitance, the conventional multilayer capacitor 100 shown in fig. 9 is configured such that: a pair of ceramic layers 112A on which two kinds of internal conductor layers 114 and 116 shown in fig. 10 are provided are alternately stacked to form a dielectric substrate 112.

The two kinds of internal conductor layers 114 and 116 are drawn out to the two side surfaces 112B and 112C of the dielectric base 112 facing each other. The terminal electrode 118 connected to the internal conductor layer 114 and the terminal electrode 120 connected to the internal conductor layer 116 are provided on the side surfaces 112B and 112C of the multilayer capacitor 100 shown in fig. 9, which face each other.

In such a conventional multilayer capacitor 100, the ESL is large, and it is difficult to reduce the voltage variation of the CPU power supply in particular.

In addition, in order to reduce ESL, laminated capacitors disclosed in Japanese patent laid-open Nos. 11-144996, 2001-284171, 2002-151349, 2002-231559, 2002-164256 and the like have been developed.

However, a multilayer ceramic capacitor capable of further reducing voltage variation of a power supply for a CPU is particularly required.

Disclosure of Invention

In view of the above circumstances, an object of the present invention is to provide a multilayer capacitor capable of significantly reducing equivalent series inductance and reducing a voltage variation of a power supply for a CPU.

In order to achieve the above object, a multilayer capacitor according to a first aspect of the present invention is a multilayer capacitor having

A dielectric layer; and

a multilayer capacitor including at least four first to fourth internal conductor layers insulated by the dielectric layers and sequentially arranged in a first to fourth order in a dielectric substrate, the multilayer capacitor comprising:

at least one cut-in portion is formed in each of the first to fourth inner conductor layers,

forming a channel portion through which a current flows in a folded manner on each of the internal conductor layers by using the cut-in portion,

currents flow in mutually opposite directions between the flow path portions of the internal conductor layers adjacent to each other in the stacking direction with the dielectric layers interposed therebetween.

When the multilayer capacitor according to the first aspect of the present invention is used, when current is applied to the multilayer capacitor, current flows in mutually opposite directions between the flow path portions above and below the dielectric layers in the stacking direction. Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, and the parasitic inductance of the multilayer capacitor itself is reduced. Therefore, the equivalent series inductance (ESL) is reduced. In addition, even in the same inner conductor layer, the ESL is further reduced because the direction of current flow is reversed between the portions of the channel portions located on both sides with the cut portions interposed therebetween.

As described above, in the multilayer capacitor according to the first aspect of the present invention, a lower ESL can be achieved, and the effective inductance can be significantly reduced. As a result, if the first aspect of the present invention is employed, the voltage fluctuation of the power supply can be reliably suppressed, and an optimum multilayer capacitor can be obtained for the power supply of the CPU.

The first inner conductor layer and the third inner conductor layer preferably have planar shapes that are point-symmetric with respect to the centers of these conductor layers.

The second inner conductor layer and the fourth inner conductor layer preferably have planar shapes that are point-symmetric with respect to the centers of these conductor layers.

Since the internal conductor layers are formed in such a pattern, the directions of currents are easily made opposite to each other between the flow path portions of the internal conductor layers adjacent to each other in the stacking direction with the dielectric layers interposed therebetween.

Preferably, the first internal conductor layer has a first lead-out portion which is led out toward the first side surface of the dielectric base,

the third inner conductor layer has a third lead-out portion that leads out toward a third side surface opposite to the first side surface of the dielectric base.

Preferably, a first terminal electrode connected to the first lead-out portion is mounted on the first side surface of the dielectric base,

the third terminal electrode connected to the third lead-out portion is mounted on the third side surface of the dielectric base.

Preferably, the second inner conductor layer has a second lead-out portion which is led out toward a second side surface different from the first side surface and the third side surface of the dielectric base,

the fourth inner conductor layer has a fourth lead-out portion that is led out toward a fourth side surface opposite to the second side surface of the dielectric base.

Preferably, a second terminal electrode connected to the second lead portion is mounted on the second side surface of the dielectric base,

a fourth terminal electrode connected to the fourth lead-out portion is attached to a fourth side surface of the dielectric base body.

Thus, by forming the terminal electrodes on the four side surfaces of the dielectric base body, respectively, the ESL can be further reduced.

Preferably, the width of the first lead-out portion is substantially the same as the entire width of the first inner conductor layer in which the cut-out portion is formed,

the width of the third lead-out portion is substantially the same as the entire width of the third inner conductor layer in which the cut-out portion is formed.

Preferably, the first terminal electrode and the third terminal electrode have widths equal to or larger than widths of the first lead portion and the third lead portion.

In this way, by widening the widths of the first lead portion and the third lead portion, the connection of these lead portions and the corresponding terminal electrodes is more reliable.

The width of the second lead-out portion is substantially the same as the width of the flow path portion isolated by the cut-out portion of the second inner conductor layer,

the width of the fourth lead-out portion may be substantially the same as the width of the flow path portion isolated by the cut portion of the fourth inner conductor layer.

The widths of the second and fourth lead-out portions may be substantially the same as the widths of the corresponding internal conductor layers.

Preferably, the second lead-out portion is led out at a substantially central portion of the second side surface, and the fourth lead-out portion is led out at a substantially central portion of the fourth side surface.

In the first aspect of the present invention, the width of the second terminal electrode is equal to or greater than the width of the second lead portion, but is narrower than the width of the second side surface,

the width of the fourth terminal electrode may be substantially the same as the width of the second terminal electrode.

In the first aspect of the present invention, the first to fourth inner conductor layers may be repeatedly laminated in the lamination direction through the dielectric layers in this order. In this case, the electrostatic capacitance of the multilayer capacitor increases, and the action of canceling the magnetic field becomes stronger, so that the inductance can be significantly reduced, and the ESL can be further reduced.

In the first aspect of the present invention, the planar shape of the cut portion is not particularly limited, but is preferably substantially L-shaped, for example. In the case of such an L-shaped cut portion, flow path portions having mutually opposite directions are easily formed.

In order to achieve the above object, a multilayer capacitor according to a second aspect of the present invention is a multilayer capacitor having

A dielectric layer; and

a multilayer capacitor including at least eight types of first to eighth inner conductor layers, which are insulated by the dielectric layers and sequentially arranged in the dielectric substrate in the order of first to eighth, wherein:

at least one cut-in portion is formed in each of the first to eighth inner conductor layers,

In the second aspect of the present invention, the eight kinds of internal conductor layers each have a cut portion, and the internal conductor layer portions around the cut portion constitute flow path portions, and current flows in opposite directions in the same plane, and flows in opposite directions between the flow path portions of another internal conductor layer adjacent to the other internal conductor layer with the dielectric layer interposed therebetween.

Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, and the parasitic inductance of the multilayer capacitor itself can be reduced. As a result, the equivalent series inductance (ESL) can be reduced.

In addition, even in the same inner conductor layer, the flow direction of the current is reversed between the flow path portions located on both sides with the cut portion interposed therebetween, so that the equivalent series inductance can be further reduced.

As described above, if the multilayer capacitor according to the second aspect of the present invention is used, ESL can be further reduced, and effective inductance can be further reduced.

Preferably, the first inner conductor layer and the fifth inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the second inner conductor layer and the sixth inner conductor layer have planar shapes point-symmetric with respect to the centers of these conductor layers,

the third inner conductor layer and the seventh inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the fourth inner conductor layer and the eighth inner conductor layer have planar shapes that are point-symmetric with respect to the centers of these conductor layers.

By forming the first to eighth inner conductor layers in such a pattern, the directions of currents can be easily made opposite to each other between the inner conductor layers adjacent in the stacking direction.

the second internal conductor layer has a second lead-out portion which is led out toward the first side surface of the dielectric base at a position different from the first lead-out portion,

the fifth internal conductor layer has a fifth lead-out portion which is led out toward a third side surface opposite to the first side surface of the dielectric base,

the sixth inner conductor layer has a sixth lead-out portion which is led out toward the third side surface of the dielectric base at a position different from the fifth lead-out portion,

the third inner conductor layer has a third lead-out portion which is led out toward a second side surface different from the first side surface and the third side surface of the dielectric base,

the fourth inner conductor layer has a fourth lead-out portion which is led out toward the second side surface of the dielectric base at a position different from the third lead-out portion,

the seventh inner conductor layer has a seventh lead-out portion which is led out toward a fourth side surface opposite to the second side surface of the dielectric base,

the eighth inner conductor layer has an eighth lead-out portion which is led out toward the fourth side surface of the dielectric base at a position different from the seventh lead-out portion.

Preferably, a first terminal electrode and a second terminal electrode connected to the first lead portion and the second lead portion, respectively, are attached to the first side surface of the dielectric base,

a third terminal electrode and a fourth terminal electrode connected to the third lead-out portion and the fourth lead-out portion, respectively, are mounted on the second side surface of the dielectric base body,

a fifth terminal electrode and a sixth terminal electrode connected to the fifth lead portion and the sixth lead portion, respectively, are mounted on the third side surface of the dielectric base,

a seventh terminal electrode and an eighth terminal electrode connected to the seventh lead portion and the eighth lead portion, respectively, are attached to a fourth side surface of the dielectric base.

By disposing the lead portions and the electrodes in this manner, two terminal electrodes can be formed on each of the four side surfaces of the dielectric base. When current is applied to the multilayer capacitor, the polarities of the adjacent terminal electrodes are different from each other, and the terminal electrodes alternate between positive and negative electrodes, so that current flows. Therefore, the magnetic fluxes generated in the respective lead portions cancel each other out by the action of the currents flowing in opposite directions in the lead portions, and the equivalent series inductance is further reduced.

Preferably, the width of each lead-out portion is 1/3 to 1/4 of the width of the flow path portion in each internal conductor layer. By forming the dimensions in this manner, a structure in which two terminal electrodes are arranged on the same side surface can be reliably realized. In addition, the internal conductor layers and the terminal electrodes can be connected more reliably.

Preferably, the first to eighth inner conductor layers are laminated in this order and repeatedly in the lamination direction through the dielectric layers.

In this case, not only the electrostatic capacitance of the multilayer capacitor is large, but also the effect of canceling magnetic fields is large, and the inductance is further reduced, so that the ESL can be further reduced.

In the second aspect of the present invention, the planar shape of the cut portion is not particularly limited, but is preferably substantially linear. In the second aspect of the present invention, even if the planar shape of the notch is made substantially linear, it is easy to form currents having mutually opposite flowing directions.

In order to achieve the above object, a multilayer capacitor according to a third aspect of the present invention is a multilayer capacitor having

A dielectric layer;

at least four first to fourth internal conductor layers insulated by the dielectric layer and sequentially arranged in the dielectric substrate in the order of first to fourth;

a fifth internal conductor layer formed on the dielectric layer on which the first internal conductor layer is formed and formed adjacent to the first internal conductor layer in the same planar direction in a pattern of insulation from the first internal conductor layer;

a sixth internal conductor layer formed on the dielectric layer on which the second internal conductor layer is formed and formed adjacent to the second internal conductor layer in the same planar direction in a pattern of insulation from the second internal conductor layer;

a seventh internal conductor layer formed on the dielectric layer on which the third internal conductor layer is formed and formed adjacent to the third internal conductor layer in the same planar direction in a pattern of insulation from the third internal conductor layer; and

a multilayer capacitor including an eighth inner conductor layer formed on a dielectric layer on which the fourth inner conductor layer is formed and formed adjacent to the fourth inner conductor layer in a same planar direction in a pattern insulating from the fourth inner conductor layer, the multilayer capacitor including:

In the multilayer capacitor according to the third aspect of the present invention, when current is applied to the multilayer capacitor, currents flow in mutually opposite directions between the flow path portions adjacent in the stacking direction through the dielectric layers. Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, and the parasitic inductance of the multilayer capacitor itself can be reduced. Therefore, the equivalent series inductance (ESL) is reduced. In addition, even in the same inner conductor layer, the flow directions of the currents are opposite between the flow path portions located on both sides with the cut portions interposed therebetween, and therefore the equivalent series inductance is further reduced.

In the third aspect of the present invention, eight kinds of internal conductor layers are stacked in four layers so as to be arranged on the same plane for each of two kinds. Therefore, a capacitor in which two sets of internal conductor layers are arranged to face each other is formed inside one dielectric substrate.

That is, in the multilayer capacitor according to the third aspect of the present invention, two multilayer capacitors according to the first aspect of the present invention are provided adjacently in the same dielectric substrate, and therefore, a lower ESL can be achieved, and the effective inductance can be significantly reduced. As a result, according to the third aspect of the present invention, the voltage fluctuation of the power supply can be suppressed reliably, and an optimum multilayer capacitor can be obtained for the power supply of the CPU.

In the third aspect of the present invention, the eight kinds of internal conductor layers are arranged so as to be arranged on the same plane for each of the two kinds, respectively, to constitute the capacitor array formed of the two sets of capacitors, so that the multilayer capacitor can be made more highly functional.

Preferably, the first inner conductor layer and the third inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the second inner conductor layer and the fourth inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the fifth inner conductor layer and the seventh inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the sixth inner conductor layer and the eighth inner conductor layer have planar shapes that are point-symmetric with respect to the centers of these conductor layers.

Further, it is preferable that the first internal conductor layer and the fifth internal conductor layer have plane shapes that are point-symmetric with respect to the center of the gap between the conductor layers,

the second inner conductor layer and the sixth inner conductor layer have plane shapes that are point-symmetric with respect to the center of the gap between these conductor layers,

the third inner conductor layer and the seventh inner conductor layer have plane shapes that are point-symmetric with respect to the center of the gap between these conductor layers,

the fourth inner conductor layer and the eighth inner conductor layer have planar shapes that are point-symmetric with respect to the center of the gap between these conductor layers.

By forming the internal conductor layers in such a pattern, the flow directions of currents can be easily made opposite to each other between the flow path portions of the internal conductor layers adjacent to each other in the stacking direction with the dielectric layers interposed therebetween.

the fifth inner conductor layer has a fifth lead-out portion which is led out toward a third side surface opposite to the first side surface of the dielectric base,

the third inner conductor layer has a third lead-out portion which is led out toward the third side surface of the dielectric base body at a position different from the fifth lead-out portion and the sixth lead-out portion,

the seventh internal conductor layer has a seventh lead-out portion which is led out toward the first side surface of the dielectric base at a position different from the first lead-out portion and the second lead-out portion,

the fourth inner conductor layer has a fourth lead-out portion which is led out toward the third side surface of the dielectric base body at a position different from the third lead-out portion, the fifth lead-out portion, and the sixth lead-out portion,

the eighth inner conductor layer has an eighth lead-out portion which is led out toward the first side surface of the dielectric base at a position different from the first, second, and seventh lead-out portions.

Preferably, a first terminal electrode connected to the first lead portion, a second terminal electrode connected to the second lead portion, a seventh terminal electrode connected to the seventh lead portion, and an eighth terminal electrode connected to the eighth lead portion are mounted on the first side surface of the dielectric base,

a third terminal electrode connected to the third lead portion, a fourth terminal electrode connected to the fourth lead portion, a fifth terminal electrode connected to the fifth lead portion, and a sixth terminal electrode connected to the sixth lead portion are mounted on the third side surface of the dielectric base body.

As a result, for example, the two terminal electrodes disposed adjacent to the side surface of the dielectric base are connected to the lead portions between the two internal conductor layers adjacent to each other with the dielectric layer interposed therebetween. Therefore, when current is applied to the multilayer capacitor, the polarities of the adjacent terminal electrodes are different from each other, and the terminal electrodes alternate between positive and negative polarities, so that current flows. Therefore, the magnetic fluxes generated in the respective lead portions cancel each other out by the action of the currents flowing in opposite directions in the lead portions, and the equivalent series inductance is reduced.

Preferably, the first to eighth lead portions have widths equal to or lower than widths of the flow path portions in the internal conductor layers. With this configuration, four terminal electrodes can be arranged on two opposing side surfaces of the dielectric base.

Preferably, the dielectric substrate has a rectangular parallelepiped shape having a second side surface and a fourth side surface different from the first side surface and the third side surface,

the first side surface and the third side surface are wider than the second side surface and the fourth side surface.

With this configuration, the total of eight lead portions led out from the eight kinds of internal conductor layers can be easily led out four each toward two long side surfaces formed among the four side surfaces of the dielectric base. Also, the polarities between adjacent terminal electrodes are different from each other. In addition, since four terminal electrodes connected to the lead-out portions of the inner conductor layers are present on each of the two long side surfaces formed out of the four side surfaces of the dielectric base body, the formed long side surfaces can be effectively used. Therefore, the multilayer capacitor can be miniaturized.

Preferably, the first to fourth inner conductor layers are laminated in this order while repeating the lamination direction a plurality of times with the dielectric layers interposed therebetween, respectively

The fifth to seventh inner conductor layers are repeatedly laminated in the lamination direction in this order through the dielectric layers.

With such a configuration, not only the electrostatic capacitance of the multilayer capacitor is increased, but also the effect of magnetic fields canceling each other is further increased, the inductance is further reduced, and the ESL can be further reduced.

Preferably, the cut portions formed in the first, fifth, third and seventh inner conductor layers are substantially L-shaped,

the cut portions formed in the second, sixth, fourth, and eighth inner conductor layers are substantially linear. In the case of the cut portions having such a shape, flow path portions having mutually opposite directions can be easily formed.

In the first to third aspects of the present invention, the width of the cut portion is 1/10 to 1/3, preferably 1/8 to 1/4 of the width of the inner conductor layer. If the width of the cut portion is too small, the insulation tends to be insufficient, and if the width of the cut portion is too large, the electrode area tends to decrease, and the capacitance tends to decrease.

Drawings

The present invention will be described in detail below with reference to the accompanying drawings. At this point in time,

fig. 1 is an exploded perspective view of a multilayer capacitor according to an embodiment of the present invention, and is a diagram showing the pattern of each internal conductor layer of the multilayer capacitor.

Fig. 2 is an oblique view of the stacked capacitor shown in fig. 1.

Fig. 3 is a sectional view taken along the line III-III shown in fig. 2.

Fig. 4 is a sectional view taken along line IV-IV shown in fig. 3.

Fig. 5 is a diagram showing an equivalent circuit of the multilayer capacitor shown in fig. 1 to 4.

Fig. 6 is a graph showing the attenuation characteristics of the example of the present invention and the comparative example.

Fig. 7 is a diagram showing an example of a circuit in which a multilayer capacitor is incorporated.

Fig. 8 is a graph showing a relationship between a current change and a voltage change in a circuit using a multilayer capacitor of the conventional example.

Fig. 9 is a perspective view of a conventional multilayer capacitor.

Fig. 10 is an exploded oblique view showing an inner conductor layer in the multilayer capacitor shown in fig. 9.

Fig. 11 is an exploded perspective view of a multilayer capacitor according to another embodiment of the present invention, each showing a pattern of an internal conductor layer of the multilayer capacitor.

Fig. 12 is an oblique view showing the stacked capacitor shown in fig. 11.

Fig. 13 is a sectional view taken along line XIII-XIII shown in fig. 12.

Fig. 14 is a diagram showing an equivalent circuit of the multilayer capacitor shown in fig. 11 to 13.

Fig. 15 is a graph showing the attenuation characteristics of the examples of the present invention and the comparative examples.

Fig. 16 is an exploded perspective view of a multilayer capacitor according to another embodiment of the present invention, each showing a pattern of an internal conductor layer of the multilayer capacitor.

Fig. 17 is an oblique view illustrating the stacked capacitor shown in fig. 16.

Fig. 18 is a sectional view taken along line XVIII-XVIII shown in fig. 17.

Fig. 19 is a diagram showing an equivalent circuit of the multilayer capacitor shown in fig. 16 to 18.

Fig. 20 is a circuit diagram in which the multilayer capacitors shown in fig. 16 to 18 are connected as a capacitor array to 2 circuits.

Fig. 21 is a graph showing the attenuation characteristics of the samples of the example of the present invention and the comparative example.

Detailed Description

Hereinafter, an embodiment of the multilayer capacitor according to the present invention will be described with reference to the drawings.

First embodiment

Fig. 1 to 5 show a multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) as an embodiment of the multilayer capacitor of the present invention. As shown in these figures, a stack of green ceramic sheets (ceramic layers 12A after firing) which are a plurality of dielectric sheets is fired to obtain a rectangular parallelepiped sintered body, and the multilayer capacitor 10 has a dielectric substrate 12 which is the sintered body as a main part.

As shown in fig. 1, 3, and 4, a planar first inner conductor layer 14 having a plane formed by the X axis and the Y axis is disposed at a predetermined height position in the lamination direction Z of the ceramic layers (dielectric layers) 12A in the dielectric base 12. A planar second internal conductor layer 16 is similarly disposed in the dielectric base body 12 below the internal conductor layer 14 with the ceramic layer 12A interposed therebetween.

Similarly, a planar third internal conductor layer 18 is disposed in the dielectric base body 12 below the second internal conductor layer 16 in the stacking direction Z with the ceramic layer 12A interposed therebetween. Similarly, a planar fourth inner conductor layer 20 is disposed below the inner conductor layers 18 in the stacking direction Z. In this way, the first to fourth internal conductor layers 14 to 20 are arranged to face each other with the ceramic layers 12A interposed therebetween in the dielectric base 12.

That is, in the present embodiment, the ceramic layers 12A, which are the dielectric sheets after firing, are sandwiched therebetween, and the first to fourth internal conductor layers 14 to 20 are sequentially arranged in the dielectric base body 12. As shown in fig. 3 and 4, the four first to fourth inner conductor layers 14 to 20 are stacked in the same order below the fourth inner conductor layer 20 in the stacking direction Z. For example, the first to fourth inner conductor layers 14 to 20 are arranged in a total of about 100 groups (three groups in the figure).

The centers of the internal conductor layers 14, 16, 18, and 20 are arranged at substantially the same positions as the center of the dielectric base 12. The vertical and horizontal dimensions of the internal conductor layers 14 to 20 are smaller than the side length of the corresponding dielectric base 12. The materials of the substantially rectangular internal conductor layers 14, 16, 18, and 20 are not only base metals, i.e., nickel alloys, copper, or copper alloys, but also materials mainly composed of these metals.

In the present embodiment, as shown in fig. 1, first to fourth cut portions 22a to 22d each having a main portion extending in the left-right direction of the X-axis direction are provided at the central portions of the inner conductor layers 14 to 20, respectively. These cut portions 22a to 22d are each substantially L-shaped. The cutting width W1 of each of the cuts 22 a-22 d is preferably 1/10-1/3 of the width WO of the inner conductor layers 14-20, and more preferably 1/8-1/4.

The first cut 22a extends from the side near the left side in the X axis direction of the first inner conductor layer 14 in the Y axis direction toward the center in the Y axis direction of the conductor layer 14, and extends from there to the right side in the Y axis direction. The second cut portion 22b extends from the side near the center in the X axis direction of the second inner conductor layer 16 in the Y axis direction to the center in the Y axis direction of the conductor layer 16, and extends from there to the left side in the Y axis direction.

The third cut portion 22c extends from the Y-axis direction depth side near the right side in the X-axis direction in the third inner conductor layer 18 to the Y-axis direction center portion of the conductor layer 18, and extends from there to the left side in the X-axis direction. The fourth cut 22d extends from the Y-axis direction depth side near the center of the fourth inner conductor layer 20 in the X-axis direction to the Y-axis direction center of the conductor layer 20, and extends rightward therefrom in the Y-axis direction.

By forming these cut portions 22a to 22d, the first to fourth flow path portions 14B to 20B through which the current flows in a folded manner are formed in the respective inner conductor layers 14 to 20. By forming these cut portions 22a to 22d, the first internal conductor layer 14 and the third internal conductor layer 18 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers. The second inner conductor layer 16 and the fourth inner conductor layer 20 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers.

As shown in fig. 1, the first internal conductor layer 14 is formed with a first lead-out portion 14A so as to lead out the entire width WO (the entire width in the Y-axis direction) of the internal conductor layer 14 in the left direction in the X-axis direction from the left end of the internal conductor layer 14. The second inner conductor layer 16 is formed with a second lead portion 16A that is led out in the forward direction from the center portion on the forward side in the Y-axis direction in the plane.

The third inner conductor layer 18 has a lead portion 18A formed so as to lead out in the right direction from a portion on the right side in the X axis direction in the plane, over the entire width WO of the inner conductor layer 18. In addition, the fourth inner conductor layer 20 is formed with a lead portion 20A which is drawn out in a depth direction from a depth-side center portion in the Y-axis direction in the plane.

As a result, the wide lead-out portions 14A and 18A drawn out toward the two first side surfaces 12B and the third side surfaces 12D facing each other on the left and right sides of the X axis in the dielectric base 12 shown in fig. 2 have the two inner conductor layers 14 and 18, respectively. The narrow lead-out portions 16A and 20A drawn out toward the two second side surfaces 12C and the fourth side surfaces 12E facing each other on the near side and the depth side of the Y axis of the dielectric base 12 have two inner conductor layers 16 and 20, respectively. The width of the lead-out portions 16A and 20A is substantially the same as the width of the flow path portion 16B or 20B, for example.

As shown in fig. 2, on the left first side surface 12B, the first terminal electrode 24 is disposed so as to extend over the entire width of the side surface 12B such that the first lead portion 14A of the first inner conductor layer 14 is connected to the first lead portion 14A over the entire width. On the right third side surface 12D, a third terminal electrode 28 is disposed so as to extend over the entire width of the side surface 12D such that the third lead portion 18A of the third inner conductor layer 18 is connected to the third lead portion 18A over the entire width.

A second terminal electrode 26 connected to the second inner conductor layer 16 through the second lead-out portion 16A is disposed on the second side surface 12C on the near side; on the fourth side surface 12E on the depth side, a fourth terminal electrode 30 connected to the fourth inner conductor layer 20 is disposed through a fourth lead portion 20A. As described above, in the present embodiment, the terminal electrodes 24 to 30 are disposed on the four side surfaces 12B to 12E of the dielectric base 12 in the shape of a rectangular parallelepiped.

The widths of the second terminal electrode 26 and the fourth terminal electrode 30 are equal to or greater than the widths of the second lead portion 16A and the fourth lead portion 20A, but are narrower than the width L of the dielectric base 12 in the X-axis direction, preferably 1/8 to 1/2 of the width L, and more preferably about 1/6 to 1/3 of the width L. The second terminal electrode 26 and the fourth terminal electrode 30 are formed on the side surfaces 12C and 12D of the dielectric base body 12 substantially at the center in the X-axis direction along the stacking direction Z.

As shown in fig. 5, in the multilayer capacitor 10 of the present embodiment, the terminal electrode 24 is connected to, for example, an electrode of a CPU so that the internal conductor layers 14 and 16 are electrodes constituting one capacitor. The terminal electrode 26 is connected to, for example, the ground side, and the terminal electrodes 24 and 26 are used with polarities opposite to each other. Similarly, the terminal electrodes 28 and 30 are used with polarities opposite to each other so that the internal conductor layers 18 and 20 serve as electrodes constituting one capacitor.

Therefore, for example, as shown in fig. 2, when the terminal electrodes 24 and 28 are positive electrodes and the terminal electrodes 26 and 30 are negative electrodes, a current flows in the clockwise direction through the flow path portions 14B and 18B of the inner conductor layers 14 and 18 connected to the terminal electrodes 24 and 28, respectively, as indicated by arrows in fig. 1. Further, a current flows in the counterclockwise direction through the flow path portions 16B, 20B of the inner conductor layers 16, 20 connected to the terminal electrodes 26, 30, respectively.

As described above, the currents flow in the mutually opposite directions between the flow path portions 14B and 16B of the internal conductor layers 14 and 16 adjacent to each other with the ceramic layer 12A interposed therebetween. Similarly, the current flows in the opposite directions between the flow path portions 16B and 18B of the internal conductor layers 16 and 18 adjacent to each other with the ceramic layer 12A interposed therebetween. Similarly, the current flows in the opposite directions between the flow path portions 18B and 20B of the internal conductor layers 18 and 20 adjacent to each other with the ceramic layer 12A interposed therebetween.

Next, the operation of the multilayer capacitor 10 of the present embodiment will be described.

According to the multilayer capacitor 10 of the present embodiment, the pair of internal conductor layers 14 and 16 serve as capacitor electrodes arranged in parallel to face each other, and similarly, the pair of internal conductor layers 18 and 20 also serve as capacitor electrodes arranged in parallel to face each other.

In the present embodiment, when the multilayer capacitor 10 is energized, currents flow in mutually opposite directions between the flow path portions 14B to 20B of the internal conductor layers 14 to 20 adjacent to each other with the ceramic layer 12A interposed therebetween. Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, so that the parasitic inductance of the multilayer capacitor 10 itself is reduced, and the equivalent series inductance (ESL) is reduced.

In addition, in the same internal conductor layers 14 to 20, the flow directions of the currents are opposite to each other between the portions of the flow path portions 14B to 20B located on both sides with the cut-in portions 22 in between, thereby further reducing the equivalent series inductance.

As described above, the multilayer capacitor 10 of the present embodiment is required to have a lower ESL and significantly reduce the effective inductance. As a result, according to the present embodiment, the vibration of the power supply voltage can be reliably suppressed, and the multilayer capacitor 10 can be obtained optimally as a power supply for a CPU.

Further, in the present embodiment, since the internal conductor layers 14 to 20 are arranged in a plurality of groups in the dielectric base body 12, the multilayer capacitor 10 has a high capacitance, and the effect of canceling out the magnetic fields is further enhanced, so that the inductance is further reduced, and the ESL is further reduced.

Next, the S21 characteristic of the S parameter of each sample was measured using a network analyzer, and the attenuation characteristic of each sample was obtained. First, the contents of the samples to be used as the respective samples will be described. That is, the capacitor is a typical conventional multilayer capacitor shown in fig. 9 as comparative example 1, and a multilayer capacitor of one embodiment shown in fig. 2 as example 1.

Here, the constant of the equivalent circuit is calculated by matching the measured value of the attenuation characteristic with the attenuation amount of the equivalent circuit in the multilayer capacitor 100 shown in fig. 7. As is clear from the data of the attenuation characteristics of the samples shown in fig. 6, the attenuation of example 1 in the high frequency band of 20MHz or higher is increased by about 15dB as compared with comparative example 1. Therefore, it can be confirmed from this data that improvement in high-frequency characteristics is seen in the embodiment.

Furthermore, the ESL calculated as above was significantly reduced to 145.2pH in example 1 as compared with 845.3pH in comparative example 1, and the effects of the present invention were confirmed by these values. The Equivalent Series Resistance (ESR) was 5.5m Ω in comparative example 1, and 7.8m Ω in example 1.

Regarding the dimensions of each sample used here, as shown in fig. 9 and 2, the width W and the length L are: in comparative example 1 and example 1, W is 1.25mm, and L is 2.0 mm. The capacitance of each sample for the test was 1.001. mu.F in comparative example 1 and 0.968. mu.F in the example.

In the multilayer capacitor 10 of the above embodiment, the number of layers is not limited to the number shown in the embodiment, and may be increased.

Second embodiment

A multilayer capacitor according to a second embodiment of the present invention will be described below with reference to the drawings. Fig. 11 to 14 show a multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) 210 according to the present embodiment. As shown in these figures, a stack of a plurality of green ceramic sheets (ceramic layers 212A after firing) as dielectric sheets is fired to obtain a rectangular parallelepiped sintered body, and the multilayer capacitor 210 has a dielectric base 212 as a main part, which is the sintered body.

As shown in fig. 11 and 13, a planar first inner conductor layer 221 having a plane formed by the X axis and the Y axis is disposed at a predetermined height position in the dielectric base body 212. In the dielectric base 212, a planar second internal conductor layer 222 is similarly disposed below the first internal conductor layer 221 with the ceramic layer (dielectric layer) 212A interposed therebetween in the lamination direction Z.

Similarly, a planar third internal conductor layer 223 is disposed in the dielectric base body 212 below the second internal conductor layer 222 in the stacking direction Z with the ceramic layer 212A interposed therebetween. Similarly, a planar fourth internal conductor layer 224 is disposed in the dielectric base body 212 below the third internal conductor layer 223 in the stacking direction Z with the ceramic layer 212A interposed therebetween.

Similarly, a fifth internal conductor layer 225, a sixth internal conductor layer 226, a seventh internal conductor layer 227, and an eighth internal conductor layer 228 formed in a planar shape are disposed in this order with the ceramic layer 212A interposed therebetween. Therefore, eight kinds of internal conductor layers from the internal conductor layer 221 to the internal conductor layer 228 are arranged to face each other with the ceramic layer 212A interposed therebetween in the dielectric base body 212.

That is, in the present embodiment, the ceramic layers 212A, which are the dielectric sheets after firing, are sandwiched therebetween, and the first to eighth internal conductor layers 221 to 228 are sequentially arranged within the dielectric base body 212. Further, as shown in fig. 13, on the lower side of the eighth internal conductor layer 228, the eight electrodes, i.e., the groups of internal conductor layers are repeated in the same order as described above, and are arranged in a total of, for example, about several tens of groups (two groups in the figure).

The centers of the internal conductor layers 221 to 228 are arranged at substantially the same positions as the center of the dielectric base body 212, and the vertical and horizontal dimensions of the internal conductor layers 221 to 228 are smaller than the side length of the corresponding dielectric base body 212. The materials of the substantially rectangular internal conductor layers 221 to 228 are not only considered to be base metals, i.e., nickel alloys, copper or copper alloys, but also considered to be materials having these metals as main components.

As shown in fig. 11, the first cut 229a1 and the eighth cut 229a2 are formed to extend from the center portion in the Y axis direction to the center portion in the X axis direction on the left side in the X axis direction in the first inner conductor layer 221 and the eighth inner conductor layer 228, respectively. In addition, the second and third cut portions 229B1 and 229B2 are formed to extend from the center portion in the X-axis direction to the center portion in the Y-axis direction on the depth side in the Y-axis direction in the second inner conductor layer 222 and the third inner conductor layer 223, respectively.

In addition, the fourth cut 229C1 and the fifth cut 229C2 are formed to extend from the center portion in the Y-axis direction to the center portion in the X-axis direction on the right side in the X-axis direction in the fourth inner conductor layer 224 and the fifth inner conductor layer 225, respectively. In addition, the sixth and seventh cut portions 229D1 and 229D2 are formed to extend from the center portion in the X-axis direction to the center portion in the Y-axis direction on the side immediately before the Y-axis direction in the sixth and seventh inner conductor layers 226 and 227, respectively.

In the present embodiment, the planar shape of the cut portions is substantially linear, and is a shape extending from the center of the end portion in the X-axis direction or the Y-axis direction of each internal conductor layer to the center portion of each conductor layer. The cut width of these cut portions is the same as that in the embodiment shown in fig. 1.

By forming these cutouts 229a1 to 229D2, the first to eighth channel sections 221B to 228B through which the current flows in a folded manner are formed in the respective inner conductor layers 221 to 228. By forming these cut portions 229a1 to 229D2, the first inner conductor layer 221 and the fifth inner conductor layer 225 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers. The second inner conductor layer 222 and the sixth inner conductor layer 226 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers.

The third inner conductor layer 223 and the seventh inner conductor layer 227 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers. The fourth inner conductor layer 224 and the eighth inner conductor layer 228 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers.

As shown in fig. 11 and 12, the first inner conductor layer 221 has a first lead portion 221A, and the first lead portion 221A is led out toward the first side surface 212B of the dielectric base 212. The second inner conductor layer 222 has a second lead-out portion 222A, and the second lead-out portion 222A is led out toward the first side surface 212B of the dielectric base 212 at a position different from the first lead-out portion 221A.

The fifth inner conductor layer 225 has a fifth lead-out portion 225A, and the fifth lead-out portion 225A is led out toward a third side surface 212D opposite to the first side surface 212B of the dielectric base 212. The sixth inner conductor layer 226 has a sixth lead-out portion 226A, and the sixth lead-out portion 226A is led out toward the third side surface 212D of the dielectric base body 212 at a position different from the fifth lead-out portion 225A.

The third inner conductor layer 223 has a third lead-out portion 223A, and the third lead-out portion 223A is led out toward a second side surface 212C different from the first side surface 212B and the third side surface 212D of the dielectric base 212. The fourth inner conductor layer 224 has a fourth lead-out portion 224A, and the fourth lead-out portion 224A is led out toward the second side surface 212C of the dielectric base body 212 at a position different from the third lead-out portion 223A.

The seventh inner conductor layer 227 has a seventh lead-out portion 227A, and the seventh lead-out portion 227A is led out toward a fourth side surface 212E on the opposite side of the second side surface 212C of the dielectric base body 212. The eighth inner conductor layer 228 has an eighth lead portion 228A, and the eighth lead portion 228A is led toward the fourth side surface 212E of the dielectric base body 212 at a position different from the seventh lead portion 227A.

The width D2 of each of the lead-out portions 221A to 228A is 1/3 to 1/4 of the width D1 of the flow path portions 221B to 228B in each of the inner conductor layers.

As shown in fig. 12, a first terminal electrode 231 and a second terminal electrode 232 connected to the first lead portion 221A and the second lead portion 222A, respectively, are attached to the first side surface 212B of the dielectric base body 212. A third terminal electrode 233 and a fourth terminal electrode 234 connected to the third lead portion 223A and the fourth lead portion 224A, respectively, are attached to the second side surface 212C of the dielectric base body 212.

A fifth terminal electrode 235 and a sixth terminal electrode 236 connected to the fifth lead-out portion 225A and the sixth lead-out portion 226A, respectively, are attached to the third side surface 212D of the dielectric base body 212. A seventh terminal electrode 237 and an eighth terminal electrode 238, which are connected to the seventh lead portion 227A and the eighth lead portion 228A, respectively, are attached to the fourth side surface 212E of the dielectric base body 212.

That is, the lead portions 221A to 228A shown in fig. 11 are led out two by two toward the four side surfaces 212B to 212E of the dielectric base body 212 shown in fig. 12, and are connected to the respective terminal electrodes 231 to 238. The width of each of the terminal electrodes 231 to 238 is equal to or greater than the width D2 of each of the lead portions 221A to 228A shown in fig. 11, but it is possible to ensure that adjacent terminal electrodes are insulated from each other.

In this way, in the present embodiment, two terminal electrodes 231 to 238 are disposed on each of the four side surfaces 212B to 212E of the dielectric base 212 in the form of a rectangular parallelepiped, that is, a hexahedron, and the terminal electrodes 231 to 238 are connected to the eight kinds of inner conductor layers 221 to 228 via the lead portions 221A to 228A, respectively.

For example, as shown in fig. 14, in the multilayer capacitor 210 of the present embodiment, every other terminal electrode 231, 233, 235, 237 is connected to an electrode of, for example, a CPU, and every other terminal electrode 232, 234, 236, 238 is connected to, for example, the ground side. Accordingly, voltages having opposite polarities to each other are applied to the terminal electrodes 231, 233, 235, 237 and the terminal electrodes 232, 234, 236, 238.

Thus, for example, as shown in fig. 12 and 14, every other terminal electrode 231, 233, 235, 237 is a plus pole, and every other terminal electrode 232, 234, 236, 238 is a minus pole. At this time, a current flows as indicated by the arrow in fig. 11.

That is, the current flows in the clockwise direction through the flow path portions 221B, 223B, 225B, 227B of the internal conductor layers 221, 223, 225, 227 connected to the terminal electrodes 231, 233, 235, 237, respectively. Further, currents flow through the flow path portions 222B, 224B, 226B, and 228B of the internal conductor layers 222, 224, 226, and 228 connected to the terminal electrodes 232, 234, 236, and 238, respectively, in the counterclockwise direction.

Thus, currents flow in mutually opposite directions between the channel portions 221B and 222B of the internal conductor layers 221 and 222 adjacent to each other with the ceramic layer 212A interposed therebetween. Similarly, the current flows in the opposite directions between the flow path portions 222B and 223B of the internal conductor layers 222 and 223 adjacent to each other with the ceramic layer 212A interposed therebetween.

Similarly, currents flow in mutually opposite directions between the flow path portions 223B and 224B of the internal conductor layers 223 and 224 adjacent to each other with the ceramic layer 212A interposed therebetween, between the flow path portions 224B and 225B of the internal conductor layers 224 and 225, between the flow path portions 225B and 226B of the internal conductor layers 225 and 226, between the flow path portions 226B and 227B of the internal conductor layers 226 and 227, between the flow path portions 227B and 228B of the internal conductor layers 227 and 228, and between the flow path portions 228B and 221B of the internal conductor layers 228 and 221.

Next, the operation of the multilayer capacitor 210 according to the present embodiment will be described.

According to the multilayer capacitor 210 of the present embodiment, when current is applied to the multilayer capacitor 210, the polarities of adjacent terminal electrodes among the terminal electrodes 231 to 238 are different from each other, and the current flows in such a manner that the polarities alternate between positive and negative. Therefore, the magnetic fluxes generated in the respective lead-out portions 221A to 228A cancel each other out by flowing currents in opposite directions between the adjacent lead-out portions, and an effect of reducing the equivalent series inductance is produced.

In the present embodiment, when current is applied to the multilayer capacitor 210, currents flow in mutually opposite directions between the flow path portions 221B to 228B of the internal conductor layers 221 to 228 adjacent to each other with the ceramic layer 212A interposed therebetween. Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, so that the parasitic inductance of the multilayer capacitor 210 itself is reduced, and the equivalent series inductance (ESL) is further reduced.

In addition, in the same internal conductor layers 221 to 228, the flow directions of the currents are opposite to each other in the portions of the channel portions 221B to 228B located on both sides with the cut-outs 229A to 229D interposed therebetween, thereby further reducing the equivalent series inductance.

As described above, the multilayer capacitor 210 of the present embodiment is intended to significantly reduce ESL and thus significantly reduce effective inductance. As a result, according to the present embodiment, the vibration of the power supply voltage can be reliably suppressed, and the multilayer capacitor 210 can be obtained optimally as a power supply for a CPU.

Further, in the present embodiment, since a plurality of eight kinds of internal conductor layers 221 to 228 are disposed in the dielectric base body 212, not only is the electrostatic capacitance of the multilayer capacitor 210 high, but also the action of canceling magnetic fields is further enhanced, the inductance is further reduced, and the ESL is further reduced.

Next, the Sz1 characteristic of the S parameter of each sample was measured by a network analyzer, and the attenuation characteristic of each sample was obtained. First, the contents of the samples to be used as the respective samples will be described. That is, the capacitor is a general multilayer capacitor shown in fig. 9 as comparative example 2, and a multilayer capacitor of the embodiment shown in fig. 12 as example 2.

Here, the constant of the equivalent circuit is calculated by matching the measured value of the attenuation characteristic with the attenuation amount of the equivalent circuit in the multilayer capacitor 100 shown in fig. 7. Further, as is clear from the data of the attenuation characteristics of the respective samples shown in fig. 15, the resonance point of example 2 is 15MHz different from 4.5MHz of comparative example 2, and the attenuation of example 2 is increased by about 15dB in comparison with comparative example 2 at a high frequency of 15MHz or more. Therefore, as can be understood from this data, improvement in high-frequency characteristics was seen in the embodiment.

In addition, the ESL measured and calculated by the impedance analyzer was significantly reduced to 105.2pH in example 2, as compared with 845.3pH in comparative example 2. The Equivalent Series Resistance (ESR) was 5.5m Ω in comparative example 2, and 8.2m Ω in example 2.

As for the dimensions of each sample used here, as shown in fig. 9 and 12, the width W and the length L are: in comparative example 2 and example 2, W is 1.25mm, and L is 2.0 mm. The capacitance of each sample for the test was 1.00. mu.F in comparative example 2 and 0.98. mu.F in example 2.

In the multilayer capacitor 210 of the above embodiment, eight kinds of internal conductor layers are formed, but the number of layers is not limited to the number shown in the embodiment, and may be increased. In the above embodiment, the adjacent terminal electrodes have different polarities from each other, but the terminal electrodes facing each other also have different polarities from each other, and the internal conductor layers are disposed in the above embodiment.

Third embodiment

Fig. 16 to 21 show a multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) 310 as a third embodiment of the multilayer capacitor according to the present invention. As shown in these figures, a stack of green ceramic sheets (ceramic layers 312A after firing) stacked in layers is fired to obtain a rectangular parallelepiped sintered body, and the multilayer capacitor 310 has a dielectric substrate 312 as a main part, which is the sintered body.

As shown in fig. 16 and 18, a planar first inner conductor layer 321 having a plane with an X axis and a Y axis is disposed at a predetermined height position in the lamination direction Z of the ceramic layers (dielectric layers) 312A in the dielectric base body 312. On the ceramic layer 312A on which the first internal conductor layer 321 is formed, a fifth internal conductor layer 325 is formed in a pattern insulated from the first internal conductor layer 321, so as to be adjacent to each other at a predetermined interval in the X-axis direction on the same plane.

The second and sixth internal conductor layers 322 and 326 are formed in a pattern corresponding to the first and fifth internal conductor layers 321 and 325, respectively, by sandwiching the ceramic layer 312A below the first and fifth internal conductor layers 321 and 325 in the stacking direction Z.

The third and seventh internal conductor layers 323 and 327 are formed in a pattern corresponding to the second and sixth internal conductor layers 322 and 326, respectively, by sandwiching the ceramic layer 312A below the second and sixth internal conductor layers 322 and 326 in the stacking direction Z.

The fourth internal conductor layer 324 and the eighth internal conductor layer 328 are formed in a pattern corresponding to the third internal conductor layer 323 and the seventh internal conductor layer 327, respectively, by sandwiching the ceramic layer 312A below the third internal conductor layer 323 and the seventh internal conductor layer 327 in the stacking direction Z.

By sandwiching the ceramic layer 312A below the fourth and eighth inner conductor layers 324 and 328 in the stacking direction Z, the groups of the first to fourth inner conductor layers 321 to 324 and the fifth to eighth inner conductor layers 325 to 328 are arranged in a plurality of groups in this order, as described above. The conductive layers 325 to 328 are not only base metals, i.e., nickel alloys, copper, or copper alloys, but also materials mainly composed of these metals.

At least one cut-out portion 329A 1-329D 2 is formed in each of the first to eighth inner conductor layers 321-328, and a flow path portion 321B-328B through which a current flows in a folded manner is formed in each of the inner conductor layers.

In the present embodiment, the cuts 329A1, 329C2, 329C1, 329A1 formed in the first, fifth, third and seventh inner conductor layers 321, 325, 323 and 327 are substantially L-shaped. The cut portions 329B1, 329D2, 329D1 and 329B2 formed in the second, sixth, fourth and eighth inner conductor layers 322, 326, 324 and 328 are substantially linear.

The cut 329a1 and the cut 329a2 have the same pattern, the cut 329B1 and the cut 329B2 have the same pattern, the cut 329C1 and the cut 329C2 have the same pattern, and the cut 329D1 and the cut 329D2 have the same pattern.

The cut portions 329A1 to 329D2 are formed in the following symmetrical relationship between the internal conductor layers. That is, the first inner conductor layer 321 and the third inner conductor layer 323 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers. In addition, the second inner conductor layer 322 and the fourth inner conductor layer 324 have a planar pattern shape that is point-symmetric with respect to the center of these conductor layers.

The fifth inner conductor layer 325 and the seventh inner conductor layer 327 have a plane pattern shape point-symmetrical to the center of these conductor layers. The sixth inner conductor layer 326 and the eighth inner conductor layer 328 have a planar pattern shape point-symmetrical to the center of these conductor layers.

Further, the first inner conductor layer 321 and the fifth inner conductor layer 325 have a planar pattern shape that is point-symmetric with respect to the center of the gap between these conductor layers. The second inner conductor layer 322 and the sixth inner conductor layer 326 have a plane pattern shape point-symmetrical to the center of the gap between these conductor layers.

The third inner conductor layer 323 and the seventh inner conductor layer 327 have a planar pattern shape that is point-symmetric with respect to the center of the gap between these conductor layers. The fourth inner conductor layer 324 and the eighth inner conductor layer 328 have a plane pattern shape that is point-symmetrical with respect to the center of the gap between these conductor layers.

By providing the cutouts 329a1 to 329D2 in the internal conductor layers in such a planar pattern shape, currents flow in mutually opposite directions between the flow path portions of the internal conductor layers adjacent in the stacking direction Z through the ceramic layers (dielectric layers) 312A. Further, currents flow in mutually opposite directions between the adjacent inner conductor layers located on the same plane.

The first inner conductor layer 321 has a first lead-out portion 321A which is led out toward the first side surface 312B of the dielectric base 312 shown in fig. 17. The fifth inner conductor layer 325 has a fifth lead-out portion 325A that is led out toward a third side surface 312D opposite to the first side surface 312B of the dielectric base 312.

The second inner conductor layer 322 has a second lead portion 322A which is led out toward the first side surface 312B of the dielectric base 312 at a position different from the first lead portion 321A. The sixth inner conductor layer 326 has a sixth lead portion 326A which is led out toward the third side surface 312D of the dielectric base 312 at a position different from that of the fifth lead portion.

The third inner conductor layer 323 has a third lead portion 323A which is led toward the third side surface 312D of the dielectric base 312 at a position different from the fifth lead portion 325A and the sixth lead portion 326A. The seventh inner conductor layer 327 has a seventh lead portion 327A which is led out toward the first side surface 312B of the dielectric base 312 at a position different from the first lead portion 321A and the second lead portion 322A.

The fourth inner conductor layer 324 has a fourth lead portion 324A which is led out toward the third side surface 312D of the dielectric base 312 at a position different from the third lead portion 323A, the fifth lead portion 325A, and the sixth lead portion 326A. The eighth inner conductor layer 328 has an eighth lead portion 328A which is led out toward the first side surface 312B of the dielectric base 312 at a position different from the first lead portion 321A, the second lead portion 322A, and the seventh lead portion 327A.

The widths of the first to eighth lead portions 321A to 328A are equal to or less than the widths of the flow path portions 321B to 328B in the internal conductor layers 321 to 328.

As shown in fig. 17, the dielectric base is in a rectangular parallelepiped shape having second and fourth sides 312C and 312E different from the first and third sides 312B and 312D. The first and third sides 312B and 312D have a width greater than the second and fourth sides 312C and 312E. For example, in the present embodiment, the width W of the side surfaces 312C and 312E is, for example, 1.25mm, whereas the length L of the two side surfaces 312B and 312D from which the lead portions 321A to 328A are drawn is, for example, 2.0 mm.

As shown in fig. 16, a first terminal electrode 331 connected to the first lead-out portion 321A, a second terminal electrode 332 connected to the second lead-out portion 322A, a seventh terminal electrode 337 connected to the seventh lead-out portion 327A, and an eighth terminal electrode 338 connected to the eighth lead-out portion 328A are attached to the first side surface 312B of the dielectric base 312.

A third terminal electrode 333 connected to the third lead portion 323A, a fourth terminal electrode 334 connected to the fourth lead portion 324A, a fifth terminal electrode 335 connected to the fifth lead portion 325A, and a sixth terminal electrode 336 connected to the sixth lead portion 326A are attached to the third side surface 312D of the dielectric base 312.

The terminal electrodes 331 to 338 are formed in four on two opposing side surfaces 312B and 312D on only one long side of the dielectric base 312, and are insulated with each other by being spaced apart from each other. Terminal electrodes are not formed on the second side 312C and the fourth side 312E.

The multilayer capacitor 310 of the present embodiment is an element incorporating two capacitors, and for example, a use example such as a circuit diagram shown in fig. 20 is considered. Specifically, the left terminal electrodes 331, 332, 333, and 334 in fig. 20 are connected to the left power source 341 and the CPU 343. That is, the terminal electrodes 331 and 333 are connected between one end of the CPU343 and the power source 341, and the terminal electrodes 332 and 334 are connected to the other end of the CPU343 and grounded.

The right terminal electrodes 335, 336, 337, and 338 in fig. 20 are connected to a right power supply 342 and a CPU 344. That is, the terminal electrodes 335 and 337 are connected between one end of the CPU344 and the power source 342, and the terminal electrodes 336 and 338 are connected to the other end of the CPU344 and grounded.

Therefore, as shown in an equivalent circuit shown in fig. 19, the terminal electrodes 331, 333, 335, 337 and the terminal electrodes 332, 334, 336, 338 are used with polarities opposite to each other. For example, as shown in fig. 17 and 19, every other terminal electrode 331, 337 on the front side surface 312B is a positive pole, and every other terminal electrode 332, 338 is a negative pole. In addition, every other terminal electrode 333, 335 on the side surface 312D on the depth side is a positive pole, and every other terminal electrode 334, 336 is a negative pole. At this time, a current flows as indicated by the arrow in fig. 16.

That is, the current flows in the clockwise direction through the flow path portions 321B, 323B, 325B, 327B of the internal conductor layers 321, 323, 325, 327 connected to the terminal electrodes 331, 333, 335, 337, respectively. Further, currents flow in the counterclockwise direction through the flow path portions 322B, 324B, 326B, 328B of the inner conductor layers 322, 324, 326, 328 connected to the terminal electrodes 332, 334, 336, 338, respectively.

As described above, in the left side portion of the dielectric substrate 312, currents flow in mutually opposite directions between the flow path portions 321B and 322B of the internal conductor layers 321 and 322 adjacent to each other with the ceramic layer 312A interposed therebetween. Similarly, the current flows in the opposite directions between the flow path portions 322B and 323B of the internal conductor layers 322 and 323 adjacent to each other with the ceramic layer 312A interposed therebetween.

Similarly, currents flow in opposite directions between the flow path portions 323B and 324B of the internal conductor layers 323 and 324 and between the flow path portions 324B and 321B of the internal conductor layers 324 and 321 adjacent to each other with the ceramic layer 312A interposed therebetween.

On the other hand, in the right side portion of the dielectric base 312, currents flow in mutually opposite directions also in the internal conductor layers 325 to 328 adjacent through the ceramic layer 312A.

Next, the operation of the multilayer capacitor 310 of the present embodiment will be described.

In the multilayer capacitor 310 of the present embodiment, two kinds of the eight kinds of the internal conductor layers 321 to 328 connected to the eight terminal electrodes 331 to 338 are disposed on the same plane. In the present embodiment, two sets of capacitors are formed in which the internal conductor layers are arranged in parallel so as to face each other.

As a result, when current is applied to the multilayer capacitor 310 of the present embodiment, the polarities of the adjacent terminal electrodes in the same side surface among the terminal electrodes 331 to 338 are different from each other, and the current flows in such a manner that the polarities alternate between positive and negative. Therefore, the magnetic fluxes generated in the respective lead-out portions 321A to 328A cancel each other out by the currents flowing in mutually opposite directions between the adjacent lead-out portions, thereby producing an effect of reducing the equivalent series inductance.

When current is applied to the multilayer capacitor 310, currents flow in mutually opposite directions between the flow path portions 321B to 324B of the adjacent internal conductor layers 321 to 224 through the ceramic layer 312A and between the flow path portions 325B to 328B of the internal conductor layers 325 to 228 in the same manner. Therefore, magnetic fluxes generated by the high-frequency current flowing through the inner conductor layers cancel each other out, so that the parasitic inductance of the multilayer capacitor 310 itself is reduced, and the equivalent series inductance (ESL) is further reduced.

In addition, in the same internal conductor layers 321 to 328, the flow directions of the currents are opposite to each other in the portions of the flow path portions 321B to 328B located on both sides with the cut-outs 329A to 329D interposed therebetween, thereby further reducing the equivalent series inductance.

As described above, the multilayer capacitor 310 of the present embodiment is intended to significantly reduce ESL and significantly reduce effective inductance. As a result, according to the present embodiment, the vibration of the power supply voltage can be reliably suppressed, and the multilayer capacitor 310 can be obtained optimally as a power supply for a CPU.

In the present embodiment, the eight kinds of internal conductor layers 321 to 328 are arranged in two kinds, respectively, on the same plane, thereby constituting a capacitor array including two sets of capacitors. Therefore, the multilayer capacitor 310 can be made more highly functional. In addition, the two long side surfaces 312B and 312D formed in the four side surfaces 312B to 312E of the dielectric base 312 have four terminal electrodes connected to the lead portions of the internal conductor layers, respectively, and thus the two long side surfaces 312B and 312D formed can be effectively used. Therefore, the multilayer capacitor 310 can be miniaturized.

In addition, in the present embodiment, since a plurality of eight kinds of internal conductor layers 321 to 328 are disposed in the dielectric base body 312, the multilayer capacitor 310 has a high capacitance, and the effect of canceling magnetic fields is further enhanced, so that the inductance is further reduced, and the ESL is further reduced.

Next, the Sz1 characteristic of the S parameter of each sample was measured by a network analyzer, and the attenuation characteristic of each sample was obtained. First, the contents of the samples to be used as the respective samples will be described. That is, the capacitor is a typical conventional multilayer capacitor shown in fig. 9 as comparative example 3, and a multilayer capacitor of the embodiment shown in fig. 17 as example 3.

Here, the constant of the equivalent circuit is calculated by matching the measured value of the attenuation characteristic with the attenuation amount of the equivalent circuit in the multilayer capacitor 100 shown in fig. 7. Further, as is clear from the data of the attenuation characteristics of the respective samples shown in fig. 21, the resonance point is about 18MHz in comparative example 3, whereas the attenuation amount of example 3 is about 15dB larger than that of comparative example 3 at a high frequency of 40MHz or more, and is as high as about 43MHz in example 3. Therefore, as can be understood from this data, improvement in high-frequency characteristics was seen in the embodiment.

Further, the ESL measured and calculated by the impedance analyzer was significantly reduced to 135.2pH in example 3, as compared with 750.5pH in comparative example 3. The Equivalent Series Resistance (ESR) was 20.5m Ω in comparative example 3, and 24.8m Ω in example 3.

As for the dimensions of each sample used here, as shown in fig. 17 and 9, the width W and the length L are: in comparative example 3 and example 3, W is 1.25mm, and L is 2.0 mm. The capacitance of each sample for the test was 0.105. mu.F in comparative example 3 and 0.102. mu.F in example 3.

In the multilayer capacitor 310 of the above embodiment, eight kinds of internal conductor layers are formed, but the number of layers is not limited to the number shown in the embodiment, and may be increased. In the above embodiment, the adjacent terminal electrodes have different polarities from each other, but the terminal electrodes facing each other also have different polarities from each other, and the internal conductor layers are disposed in the above embodiment.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A multilayer capacitor is provided with

A dielectric layer; and

currents flow in mutually opposite directions between the flow path portions of the internal conductor layers adjacent to each other in the stacking direction with the dielectric layers interposed therebetween,

the first inner conductor layer and the third inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

the first internal conductor layer has a first lead-out portion which is led out toward the first side surface of the dielectric base,

the third inner conductor layer has a third lead-out portion which is led out toward a third side surface opposite to the first side surface of the dielectric base,

the second inner conductor layer has a second lead-out portion which is led out toward a second side surface different from the first side surface and the third side surface of the dielectric base,

2. A stacked capacitor as claimed in claim 1, wherein:

the width of the first lead-out portion is substantially the same as the entire width of the first inner conductor layer in which the cut-out portion is formed,

3. A stacked capacitor as claimed in claim 2, wherein:

a first terminal electrode connected to the first lead-out portion is mounted on the first side surface of the dielectric base,

4. A stacked capacitor as claimed in claim 3, wherein:

the first terminal electrode and the third terminal electrode have widths equal to or greater than widths of the first lead portion and the third lead portion.

5. A stacked capacitor as claimed in claim 4, wherein:

a second terminal electrode connected to the second lead portion is mounted on the second side surface of the dielectric base,

6. A stacked capacitor as claimed in claim 5, wherein:

the width of the fourth lead-out portion is substantially the same as the width of the flow path portion isolated by the cut portion of the fourth inner conductor layer.

7. A stacked capacitor as claimed in claim 6, wherein:

the second lead-out portion is led out at a substantially central portion of the second side surface,

the fourth lead-out portion is led out at a substantially central portion of the fourth side surface.

8. A stacked capacitor as claimed in claim 7, wherein:

the width of the second terminal electrode is equal to or greater than the width of the second lead portion, but is narrower than the width of the second side surface,

the width of the fourth terminal electrode is substantially the same as the width of the second terminal electrode.

9. A multilayer capacitor according to any one of claims 1 to 8, wherein:

the first to fourth inner conductor layers are repeatedly laminated in the lamination direction in this order through the dielectric layers.

10. A multilayer capacitor according to any one of claims 1 to 8, wherein:

the planar shape of the cut-in portion is substantially L-shaped.

11. A stacked capacitor as claimed in claim 10, wherein:

the width of the cut part is 1/10-1/3 of the width of the inner conductor layer.

12. A multilayer capacitor is provided with

A dielectric layer; and

forming at least one cut portion in each of the first to eighth inner conductor layers, forming a flow path portion through which a current flows in a folded manner on each of the inner conductor layers by the cut portion,

13. A stacked capacitor as claimed in claim 12, wherein:

the first inner conductor layer and the fifth inner conductor layer have plane shapes point-symmetric with respect to the center of these conductor layers,

14. A stacked capacitor as claimed in claim 12, wherein:

the width of each cut is 1/3-1/4 of the width of the flow path section in each internal conductor layer.

15. A stacked capacitor as claimed in claim 12, wherein:

a first terminal electrode and a second terminal electrode connected to the first lead portion and the second lead portion, respectively, are mounted on the first side surface of the dielectric base,

16. A multilayer capacitor according to any one of claims 12 to 15, wherein:

the first to eighth inner conductor layers are repeatedly laminated in the lamination direction in this order through the dielectric layers.

17. A multilayer capacitor according to any one of claims 12 to 15, wherein:

the planar shape of the cut-in part is linear.

18. A stacked capacitor as claimed in claim 17, wherein:

19. A multilayer capacitor is provided with

A dielectric layer;

20. A stacked capacitor as claimed in claim 19, wherein:

21. A stacked capacitor as claimed in claim 19, wherein:

the first inner conductor layer and the fifth inner conductor layer have plane shapes that are point-symmetric with respect to the center of the gap between these conductor layers,

22. A stacked capacitor as claimed in claim 19, wherein:

23. A stacked capacitor as claimed in claim 22, wherein:

the width of each of the first to eighth lead-out portions is equal to or less than the width of the flow path portion in each of the internal conductor layers.

24. A stacked capacitor as claimed in claim 22, wherein:

the dielectric substrate has a rectangular parallelepiped shape having a second side surface and a fourth side surface different from the first side surface and the third side surface,

25. A stacked capacitor as claimed in claim 24, wherein:

a first terminal electrode connected to the first lead portion, a second terminal electrode connected to the second lead portion, a seventh terminal electrode connected to the seventh lead portion, and an eighth terminal electrode connected to the eighth lead portion are mounted on the first side surface of the dielectric base,

a third terminal electrode connected to the third lead-out portion, a fourth terminal electrode connected to the fourth lead-out portion, a fifth terminal electrode connected to the fifth lead-out portion, and a sixth terminal electrode connected to the sixth lead-out portion are mounted on a third side surface of the dielectric base body,

26. a multilayer capacitor as claimed in any one of claims 19 to 25, wherein:

the first to fourth inner conductor layers are repeatedly laminated in the lamination direction in this order through the dielectric layers, and the first to fourth inner conductor layers are laminated in this order

27. A multilayer capacitor as claimed in any one of claims 19 to 25, wherein:

the cut portions formed in the first, fifth, third and seventh inner conductor layers are substantially L-shaped,

the cut portions formed in the second, sixth, fourth, and eighth inner conductor layers are substantially linear.

28. A stacked capacitor as claimed in claim 27, wherein: