JP3847234B2 - Multilayer capacitor - Google Patents

Description

【００７３】
この表１で、Ｃは静電容量であり、ＥＳＲは等価直列抵抗である。また、ここで用いた各試料の寸法としては、図１６及び図２に示すように、一対の内部導体が引き出されている誘電体素体の側面間の距離を寸法Ｌとし、一対の内部導体が引き出された誘電体素体の側面に対して直交する側面間の距離を寸法Ｗとした時に、従来例がＬ＝２．０ｍｍでＷ＝ｌ．２５ｍｍであった。また、実施例は、Ｌ＝１．６ｍｍでＷ＝１．６ｍｍであった。
【００７４】
尚、上記実施の形態に係る積層コンデンサ１０では、４層づつで二組の計８層を有する構造とされているものの、層数はこれらの数に限定されずさらに多数とし、例えば層数を例えば数十或いは数百としても良い。また、上記実施の形態の内の第２の実施の形態以降には、分割導体がそれぞれ２つづつ或いは３つづつ配置される構造が示されているが、これら分割導体を４つづつ以上配置するようにしても良い。
【００７５】
【発明の効果】
本発明によれば、ＥＳＬを大幅に低減した積層コンデンサを提供することが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る積層コンデンサの分解斜視図である。
【図２】本発明の第１の実施の形態に係る積層コンデンサを示す斜視図である。
【図３】本発明の第１の実施の形態に係る積層コンデンサを示す断面図であって、図２の３−３矢視線断面に対応する図である。
【図４】本発明の第１の実施の形態に係る積層コンデンサの等価回路図である。
【図５】本発明の第２の実施の形態に係る積層コンデンサの分解斜視図である。
【図６】本発明の第２の実施の形態に係る積層コンデンサを示す断面図であって、図２の３−３矢視線断面に対応する図である。
【図７】本発明の第３の実施の形態に係る積層コンデンサの分解斜視図である。
【図８】本発明の第４の実施の形態に係る積層コンデンサの分解斜視図である。
【図９】本発明の第５の実施の形態に係る積層コンデンサの分解斜視図である。
【図１０】本発明の第６の実施の形態に係る積層コンデンサの分解斜視図である。
【図１１】ネットワークアナライザへの各試料の接続を示す回路図であって、（Ａ）は従来例の接続を示す図であり、（Ｂ）は実施例の接続を示す図である。
【図１２】各試料の減衰特性を表すグラフを示した図である。
【図１３】従来例の積層コンデンサを採用した回路図である。
【図１４】従来例の積層コンデンサを採用した回路における電流変動と電圧変動との関係を表すグラフを示した図である。
【図１５】従来例に係る積層コンデンサの等価回路図である。
【図１６】従来例に係る積層コンデンサを示す斜視図である。
【図１７】従来例に係る積層コンデンサの内部導体の部分を示す分解斜視図である。
【符号の説明】
１０ 積層コンデンサ
１２ 誘電体素体
１２Ｂ 側面
１２Ｃ 側面
１２Ｄ 側面
１２Ｅ 側面
２１、２２ 内部電極（第１内部導体）
２３、２４ 内部電極（第２内部導体）
３１、３２ 端子電極（第１端子電極）
３３、３４ 端子電極（第２端子電極）
４１〜４４ 分割導体（第１内部導体）
４５〜４８ 分割導体（第２内部導体）
５１〜５６ 分割導体（第１内部導体）
５７〜６２ 分割導体（第２内部導体）
７１〜７４ 分割導体（第１内部導体）
７５〜７８ 分割導体（第２内部導体）
８１〜８４ 分割導体（第１内部導体）
８５〜８８ 分割導体（第２内部導体）
９１、９２ 内部電極（第１内部導体）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer capacitor having a significantly reduced equivalent series inductance (ESL), and is particularly suitable for a multilayer ceramic capacitor used as a decoupling capacitor.
[0002]
[Prior art]
In recent years, a CPU (main processing unit) used in an information processing apparatus has an increased operating frequency and a significant increase in current consumption due to improvement in processing speed and higher integration. Along with this, the operating voltage tends to decrease due to the reduction in power consumption. Therefore, a large current fluctuation occurs at a higher speed in the power source for supplying power to the CPU, and it is very difficult to suppress the voltage fluctuation accompanying the current fluctuation within the allowable value of the power source.
[0003]
For this reason, as shown in FIG. 13, a multilayer capacitor 100 called a decoupling capacitor is connected to a power source 102 and is frequently used as a countermeasure for stabilizing the power source. Then, current is supplied from the multilayer capacitor 100 to the CPU 104 by quick charge / discharge when the current fluctuates at a high speed, thereby suppressing the voltage fluctuation of the power source 102.
[0004]
[Problems to be solved by the invention]
However, as the operating frequency of today's CPUs further increases, current fluctuations become faster and larger, and the equivalent series inductance (ESL) possessed by the multilayer capacitor 100 shown in FIG. It has come to greatly affect the voltage fluctuation of.
[0005]
That is, in the conventional multilayer capacitor 100 used in the power supply circuit of the CPU 104 shown in FIG. 13, the ESL which is the parasitic component shown in FIG. 15 representing the equivalent circuit is high, and therefore the fluctuation of the current I shown in FIG. Along with this, this ESL inhibits charging / discharging of the multilayer capacitor 100. For this reason, similarly to the above, the fluctuation of the voltage V of the power supply tends to become large as shown in FIG.
[0006]
This is because the voltage fluctuation at the time of charging and discharging, which is a current transient, is approximated by the following formula 1, and the level of ESL is related to the magnitude of the voltage fluctuation of the power supply.
dV = ESL · di / dt Equation 1
Here, dV is a voltage fluctuation (V) at the time of transition, i is a current fluctuation amount (A), and t is a fluctuation time (second).
[0007]
The conventional multilayer capacitor shown in FIG. 16 has a structure in which a pair of ceramic layers 112A each provided with two types of internal conductors 114 and 116 shown in FIG. It has become. Further, the two types of inner conductors 114 and 116 are respectively drawn out to the two side surfaces 112B and 112C of the dielectric element body 112 facing each other, and are connected to the terminal electrodes 118 and 120 disposed outside the dielectric element body 112. Each was connected.
In consideration of the above facts, the present invention has an object to provide a multilayer capacitor in which ESL is greatly reduced.
[0008]
[Means for Solving the Problems]
  The multilayer capacitor according to claim 1 is a multilayer capacitor in which a plurality of internal conductors are respectively disposed in a form sandwiched between dielectric sheets in a dielectric body formed by laminating a plurality of dielectric sheets,
  Each of the two sides of the dielectric body facing each otherWithdrawalA pair of first inner conductors to be ejected;
  A pair of first inner conductors are drawn on two opposite sides of a dielectric body different from the two sides drawn out.WithdrawalA pair of second inner conductors to be ejected;
  The above-mentioned plurality of inner conductors are configured,
  One of the other inner conductors is disposed between one of the pair of first inner conductors and the pair of second inner conductors.,
  At least one of the pair of first inner conductors or the pair of second inner conductors is linearly extended alongside each other, and is divided so as to be opposed to each other in the stacking direction. A plurality of divided conductors protruding alternately on two opposite sides of the element bodyA multilayer capacitor,
  A pair of first inner conductors respectively disposed on two opposite sides of the dielectric bodyNisoA pair of first terminal electrodes connected to each other;
  A pair of second inner conductors disposed on two opposite sides of the dielectric body different from the two sides on which the first terminal electrode is arrangedNisoA pair of second terminal electrodes connected to each other;
  It is characterized by providing.
[0009]
  The multilayer capacitor according to claim 1 has a configuration in which a plurality of internal conductors are respectively disposed in a dielectric body formed by laminating a plurality of dielectric sheets so as to be sandwiched between the dielectric sheets. is doing. In addition, a pair of first inner conductors are respectively provided on two opposite sides of the dielectric body.WithdrawalA pair of second inner conductors are respectively provided on two opposite side surfaces of the dielectric body different from the two side surfaces from which the pair of first inner conductors are drawn out.WithdrawalIt has been kicked out.
  That is, the plurality of inner conductors are constituted by the pair of first inner conductors and the pair of second inner conductors, and between one inner conductor of the pair of first inner conductors and the pair of second inner conductors. Any one of the other inner conductors is arranged.
[0010]
For example, since one second inner conductor is sandwiched between the pair of first inner conductors, the pair of first inner conductors have the same polarity, and the pair of first inner conductors are respectively opposite to each other of the dielectric element body. Since the structure is drawn to the side surfaces, currents flow in opposite directions in the pair of first inner conductors. On the other hand, in the pair of second inner conductors, currents flow in opposite directions from each other for the same reason.
[0011]
Therefore, not only does the current flow between the pair of first inner conductors reverse, but also cancels the magnetic field, but also the current flows between the pair of second inner conductors in the reverse direction cancels the magnetic field. Effect occurs. As the magnetic field canceling action occurs between these internal conductors, the parasitic inductance of the multilayer capacitor itself can be reduced, and the effect of reducing the equivalent series inductance is produced.
[0012]
As described above, according to the multilayer capacitor in accordance with the present invention, the multilayer capacitor is significantly reduced in ESL so as to be suitable as a decoupling capacitor, and the attenuation amount in the high frequency band increases. Voltage fluctuation can be suppressed, and a higher effect can be obtained in the power supply of the CPU.
[0013]
  Furthermore, according to the multilayer capacitor in accordance with the present invention, the pair of first inner conductors are disposed on two mutually opposing side surfaces of the dielectric body.NisoAt least a pair of first terminal electrodes connected to each other and a pair of second inner conductors disposed on two mutually facing side surfaces of a dielectric body different from the side surface on which the first terminal electrodes are disposed.NisoAnd a pair of second terminal electrodes connected to each other.
[0014]
  That is, a pair of first terminal electrodes facing each other is connected to the outside of the multilayer capacitor in a form having the same polarity, and a pair of second terminal electrodes facing each other is formed in a form having the same polarity. By being connected to the outside of the multilayer capacitor, the pair of first inner conductors have the same polarity, and the pair of second inner conductors have the same polarity.This claimThe effect of this can be achieved more reliably.
[0015]
  On the other hand, this claimAccording to the multilayer capacitor,oneAt least one of the pair of first inner conductors or the pair of second inner conductors is formed so as to extend in a straight line along with each other and to be opposed to each other in the stacking direction. A plurality of divided conductors protruding alternately on two opposite sides of the element bodyTo beYes.
[0016]
That is, the current flows in the opposite direction between a plurality of pairs of divided conductors obtained by dividing the pair of first inner conductors, and the current is reversed between a plurality of pairs of divided conductors obtained by dividing the pair of second inner conductors. Not only does the magnetic field cancel each other, but also the current flows in the opposite direction between the adjacent split conductors on the same plane, thereby canceling the magnetic field. Occurs.
As a result, as the magnetic field canceling action occurs between these divided conductors, the parasitic inductance of the multilayer capacitor itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0017]
  Claim2According to the multilayer capacitor according to claim1'sIn addition to the configuration similar to the multilayer capacitor, the dielectric body is configured to be formed in a rectangular parallelepiped shape.
  In other words, the dielectric sheets are each formed in a quadrilateral shape such as a rectangle, and the dielectric sheets are laminated to form a dielectric element body in a rectangular parallelepiped shape. For this reason, since it has a pair of 1st inner conductors and a pair of 2nd inner conductors which were each pulled out to two sides of a dielectric element body, it has four sides optimal from a viewpoint of productivity. Since the inner conductor lead-out portions are provided on all the side surfaces of the dielectric body formed in the rectangular parallelepiped shape, the effect of reducing the ESL is maximized.
[0018]
  Claim3According to the multilayer capacitor according to claim 1,And claim 2In addition to the same structure as the multilayer capacitor, a plurality of pairs of first inner conductors and second inner conductors are disposed in the dielectric body.
  Therefore, by arranging a plurality of pairs of the first inner conductor and the second inner conductor in the dielectric body, not only the capacitance of the multilayer capacitor according to the present invention is increased, but also the action of canceling the magnetic field is further increased. As a result, the inductance is greatly reduced and the ESL is further reduced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of a multilayer capacitor according to the present invention will be described with reference to the drawings.
A multilayer ceramic capacitor (hereinafter simply referred to as a multilayer capacitor) 10 which is a multilayer capacitor according to the present embodiment is shown in FIGS. As shown in these figures, the main part is a dielectric body 12 that is a rectangular parallelepiped sintered body obtained by firing a laminate in which a plurality of ceramic green sheets as dielectric sheets are laminated. A multilayer capacitor 10 is configured. In the dielectric body 12, an inner conductor 21, an inner conductor 23, an inner conductor 22 and an inner conductor 24, each formed in a substantially square shape, are arranged in order from the top, and between the inner conductors, Ceramic layers 12A are respectively disposed.
[0020]
As described above, in the present embodiment, the ceramic layer 12A, which is a fired dielectric sheet, is sandwiched between the four layers, and the four types of internal conductors 21, 23, 22, 24 are sequentially provided in the dielectric body 12. Further, on the lower side of the inner conductor 24, as shown in FIG. 3, these four kinds of inner conductors 21, 23, 22, 24 are repeated in the same order as described above, and these sets are, for example, Two sets in total are arranged. In addition, as a material of these internal conductors 21-24, not only nickel, nickel alloy, copper, or a copper alloy which are base metal materials can be considered but the material which has these metals as a main component can be considered.
[0021]
Further, as shown in FIGS. 1 to 3, the left portion of the inner conductor 21 is formed with a lead portion 21 </ b> A that is drawn to the left side surface 12 </ b> B (shown in FIG. 2) of the dielectric body 12. The inner conductor 21 extends from the drawn side surface 12B toward the opposite side surface 12D (shown in FIG. 2).
At the front side portion of the inner conductor 23 arranged below the inner conductor 21, a lead portion 23 </ b> A that is drawn out to the front side surface 12 </ b> C (shown in FIG. 2) of the dielectric body 12 is formed. The inner conductor 23 extends from the drawn side surface 12C toward the opposite side surface 12E (shown in FIG. 2).
[0022]
On the right side portion of the inner conductor 22 disposed below the inner conductor 23, a lead-out portion 22A that is drawn out to the right side surface 12D of the dielectric element body 12 is formed. The inner conductor 22 extends toward the opposite side surface 12B.
At the back side portion of the internal conductor 24 arranged below the internal conductor 22, a lead portion 24 </ b> A that is drawn out to the side surface 12 </ b> E on the back side of the dielectric element body 12 is formed. This internal conductor 24 extends from 12E toward the opposing side surface 12C.
[0023]
That is, in FIGS. 1 and 3, the internal conductor 23 is disposed between the internal conductor 21 and the internal conductor 22 constituting the pair of first internal conductors, and the internal conductor 23 constituting the pair of second internal conductors. The inner conductor 22 is disposed between the inner conductor 24 and the inner conductor 24. Further, the four types of internal conductors 21, 23, 22, and 24 shown in FIG. 3 are sequentially arranged below the internal conductor 24 in the same manner as described above.
[0024]
Therefore, in the present embodiment, the inner conductors 21 and 22 are drawn out to the two opposite side surfaces 12B and 12D of the dielectric element body 12, respectively, and the inner conductors 23 and 24 are The two side surfaces 12C and 12E of the dielectric element body 12 that are different from the two side surfaces 12B and 12D that are drawn out 22 are opposed to each other. That is, the lead portions 21A, 23A, 22A, and 24A of these four types of inner conductors 21, 23, 22, and 24 are projected onto the dielectric sheet in the stacking direction indicated by the arrow Z in FIG. 1 and FIG. It is arranged on each side surface of the dielectric body 12 so that the positional relationship is not satisfied.
[0025]
On the other hand, the terminal electrode 31 shown in FIGS. 2 and 3 is disposed outside the dielectric element body 12 so as to be positioned on the side surface 12B of the dielectric element body 12 so as to be connected to the lead portion 21A of the inner conductor 21. In addition, the terminal electrode 32 is also disposed outside the dielectric element body 12 so as to be positioned on the side surface 12D of the dielectric element body 12 so as to be connected to the lead portion 22A of the inner conductor 22.
[0026]
Further, the terminal electrode 33 is disposed outside the dielectric element body 12 so as to be positioned on the side surface 12C of the dielectric element body 12 so as to be connected to the lead portion 23A of the inner conductor 23. Similarly, the terminal electrode 34 is disposed outside the dielectric element body 12 so as to be positioned on the side surface 12E of the dielectric element body 12 so as to be connected to the 24 lead portions 24A.
[0027]
That is, in the present embodiment, the terminal electrode 31 and the terminal electrode 32 that are a pair of first terminal electrodes are respectively disposed on the two side surfaces 12B and 12D of the dielectric element body 12 that face each other. The second terminal electrode 33 and the terminal electrode 34 are formed on the two side surfaces 12C and 12E of the dielectric body 12 that are different from the two side surfaces 12B and 12D on which the terminal electrode 31 and the terminal electrode 32 are disposed. Each is arranged.
[0028]
As described above, in the present embodiment, the inner conductors 21 to 24 constitute electrodes facing each other of the capacitor, and the terminal electrodes 31 to 34 connected to the inner conductors 21 to 24 on the side surfaces 12B to 12E of the multilayer capacitor 10. Are arranged to constitute an equivalent circuit as shown in FIG. For this reason, the multilayer capacitor 10 according to the present embodiment has a structure in which the terminal electrodes 31 to 34 are disposed on all four side surfaces 12B to 12E of the dielectric body 12 that is a hexahedron shape that is a rectangular parallelepiped. ing.
[0029]
Next, the operation of the multilayer capacitor 10 according to the present embodiment will be described.
According to the multilayer capacitor 10 according to the present embodiment, a plurality of dielectric sheets each serving as the ceramic layer 12A are stacked and sandwiched between these ceramic layers 12A in a dielectric body 12 formed in a rectangular parallelepiped shape. A plurality of internal conductors are arranged in a shape.
[0030]
In addition, a pair of inner conductors 21 and 22 are drawn out to the two side surfaces 12B and 12D opposite to each other of the dielectric body 12, respectively, and a different dielectric from the two side surfaces 12B and 12D from which the pair of inner conductors 21 and 22 are drawn. A pair of internal conductors 23 and 24 are drawn out from the two side surfaces 12C and 12E of the body element body 12 facing each other.
That is, the pair of inner conductors 21 and 22 and the pair of inner conductors 23 and 24 constitute the plurality of inner conductors. In the present embodiment, the inner conductor 23 is disposed between the inner conductors 21 and 22, An internal conductor 22 is disposed between the internal conductors 23 and 24.
[0031]
Further, in the present embodiment, the pair of terminal electrodes 31 and 32 respectively disposed on the two opposite side surfaces 12B and 12D of the dielectric body 12 are connected to the pair of internal conductors 21 and 22, respectively. ing. In addition, the pair of terminal electrodes 33 and 34 respectively disposed on the two side surfaces 12C and 12E of the dielectric element body 12 that are different from the side surfaces 12B and 12D on which the terminal electrodes 31 and 32 are disposed are the above-described pair of terminals. Are connected to the inner conductors 23 and 24, respectively.
[0032]
That is, for example, the pair of inner conductors 21 and 22 are respectively drawn out to the two opposite side surfaces 12B and 12D of the dielectric body 12 and connected to the pair of terminal electrodes 31 and 32 facing each other. Instead, one internal conductor 23 is sandwiched between the internal conductors 21 and 22 as described above. If the pair of terminal electrodes 31 and 32 are connected to the external wiring or the like of the multilayer capacitor 10 so as to exhibit the function as a capacitor, the pair of inner conductors 21, In FIG. 22, currents flow in opposite directions as indicated by arrows in FIG. 1, and the pair of internal conductors 21 and 22 have the same polarity.
[0033]
On the other hand, in the pair of internal conductors 23 and 24, if the pair of terminal electrodes 33 and 34 facing each other are connected to the wiring or the like outside the multilayer capacitor 10 so as to have the same polarity, the pair of terminal electrodes 33 and 34 In the inner conductors 23 and 24, for the same reason, currents flow in opposite directions as shown by arrows in FIG. 1, and the pair of inner conductors 23 and 24 have the same polarity.
[0034]
Therefore, not only does the current flow between the pair of inner conductors 21 and 22 in the opposite direction cause the magnetic field to cancel, but also the current flows between the pair of inner conductors 23 and 24 in the opposite direction. The effect of canceling out will occur. As the magnetic field canceling action occurs between these internal conductors, the parasitic inductance of the multilayer capacitor 10 itself can be reduced, and the effect of reducing the equivalent series inductance is produced.
[0035]
As described above, according to the multilayer capacitor 10 according to the present embodiment, the multilayer capacitor 10 can be significantly reduced in ESL so as to be suitable as a decoupling capacitor, and the attenuation in the high frequency band is increased. As a result, voltage fluctuations of the power supply can be suppressed, and a higher effect can be obtained in the CPU power supply.
[0036]
Further, the inner conductors 21 and 22 that are the first inner conductors and the inner conductors 23 and 24 that are the second inner conductors are arranged in pairs in the dielectric element body 12, respectively. Not only the capacitance of the multilayer capacitor 10 is increased, but also the action of canceling out the magnetic field is further increased, and the multilayer capacitor 10 is further reduced in inductance and further reduced in ESL.
[0037]
On the other hand, when manufacturing the multilayer capacitor 10 according to the present embodiment, the dielectric body 12 was formed in a rectangular parallelepiped shape by laminating dielectric sheets each formed in a quadrilateral shape such as a rectangle.
As a result, the present embodiment has a pair of internal conductors 21 and 22 and a pair of internal conductors 23 and 24 that are drawn out from each of the two side surfaces of the dielectric element body 12. ESL is reduced because the lead portions of the internal conductors 21 to 24 are provided on all the side surfaces 12B to 12E of the dielectric element body 12 formed in a rectangular parallelepiped shape having four side surfaces 12B to 12E that are optimal from the viewpoint. The maximum effect is achieved.
[0038]
Next, a second embodiment of the multilayer capacitor according to the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated in 1st Embodiment, and the overlapping description is abbreviate | omitted.
In the first embodiment, each internal conductor is integrally formed. In the present embodiment, as shown in FIGS. 5 and 6, the internal structure of the first embodiment is used. A plurality of (two in this embodiment) divisions in which the conductor 21 is divided so as to extend side by side and alternately drawn out on the two side surfaces 12B and 12D (shown in FIG. 2) facing each other of the dielectric element body 12. Conductors 41 and 42 are provided. Also, the inner conductor 22 of the first embodiment is similarly divided into two extending side by side and alternately on the two side surfaces 12B and 12D of the dielectric element body 12 facing each other, and the reverse of the above A plurality of (two in this embodiment) divided conductors 43 and 44 are drawn out.
[0039]
That is, the divided conductor 41 and the divided conductor 43 that are positioned to face each other in the stacking direction are drawn out to the two side surfaces 12B and 12D that face each other. The divided conductor 42 and the divided conductor 44 that are positioned are drawn out to the two side surfaces 12D and 12B that face each other. Therefore, in the present embodiment, the divided conductor 41 and the divided conductor 44 are connected to the terminal electrode 31 shown in FIG. 2, respectively, and the divided conductor 42 and the divided conductor 43 are connected to the terminal electrode 32 shown in FIG. Will be.
[0040]
On the other hand, the inner conductor 23 of the first embodiment is also divided so as to extend side by side, and alternately drawn out to the two side surfaces 12C and 12E (shown in FIG. 2) of the dielectric element body 12 facing each other. A plurality (two in this embodiment) of divided conductors 45 and 46 are provided. Similarly, the inner conductor 24 of the first embodiment is also divided into two extending side by side and alternately on the two side surfaces 12C and 12E facing each other of the dielectric element body 12, and the reverse of the above. A plurality of (two in the present embodiment) divided conductors 47 and 48 drawn out to.
[0041]
That is, the divided conductor 45 and the divided conductor 47 that are positioned opposite to each other in the stacking direction are drawn out to the two side surfaces 12C and 12E that face each other. The divided conductor 46 and the divided conductor 48 that are positioned are drawn out to the two side surfaces 12E and 12C that face each other. For this reason, in this embodiment, the divided conductor 45 and the divided conductor 48 are connected to the terminal electrode 33 shown in FIG. 2, respectively, and the divided conductor 46 and the divided conductor 47 are connected to the terminal electrode 34 shown in FIG. Will be.
[0042]
From the above, between the split conductors 41 and 42 and the split conductors 43 and 44, a current flows in the opposite direction as shown by the arrow in FIG. 5, and between the split conductors 45 and 46 and the split conductors 47 and 48. Thus, the currents flow in the opposite directions as shown by the arrows in FIG. 5 not only have the effect of canceling the magnetic fields, but also the adjacent divided conductors 41 and 42 that extend side by side on the same plane. In the divided conductors 43 and 44, the divided conductors 45 and 46, and the divided conductors 47 and 48, the current flows in the opposite direction, so that the action of canceling the magnetic field is generated.
[0043]
As a result, as the magnetic field canceling action occurs between these internal conductors, the parasitic inductance of the multilayer capacitor 10 itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0044]
Next, a third embodiment of the multilayer capacitor according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated in 1st Embodiment, and the overlapping description is abbreviate | omitted.
In the present embodiment, as shown in FIG. 7, the inner conductors 21 of the first embodiment are divided so as to extend side by side, and the two side surfaces 12B and 12D of the dielectric body 12 facing each other. A plurality (three in this embodiment) of divided conductors 51, 52, and 53 are alternately drawn (shown in FIG. 2).
[0045]
Also, the inner conductor 22 of the first embodiment is similarly divided into two extending side by side and alternately on the two side surfaces 12B and 12D of the dielectric element body 12 facing each other, and the reverse of the above A plurality (three in this embodiment) of divided conductors 54, 55, and 56 are drawn out.
[0046]
That is, the divided conductor 51 and the divided conductor 54 that are positioned to face each other in the stacking direction are drawn out to the two side surfaces 12B and 12D that face each other. The divided conductor 52 and the divided conductor 55 that are positioned are drawn out to the two side surfaces 12D and 12B that face each other, and the divided conductor 53 and the divided conductor 56 that are also positioned to face each other in the stacking direction. Are drawn out to the two side surfaces 12B and 12D facing each other.
For this reason, in this embodiment, the divided conductors 51, 53, and 55 are connected to the terminal electrode 31 shown in FIG. 2, respectively, and the divided conductors 52, 54, and 56 are connected to the terminal electrode 32 shown in FIG. Will be.
[0047]
On the other hand, the inner conductor 23 of the first embodiment is also divided so as to extend side by side, and alternately drawn out to the two side surfaces 12C and 12E (shown in FIG. 2) of the dielectric element body 12 facing each other. A plurality (three in this embodiment) of divided conductors 57, 58, and 59 are provided. Similarly, the inner conductor 24 of the first embodiment is also divided into two extending side by side and alternately on the two side surfaces 12C and 12E facing each other of the dielectric element body 12, and the reverse of the above. A plurality (three in this embodiment) of divided conductors 60, 61, 62 are drawn out.
[0048]
That is, the divided conductor 57 and the divided conductor 60 that are positioned to face each other in the stacking direction are drawn out to the two side surfaces 12C and 12E that face each other, and are also opposed to each other in the stacking direction. The divided conductor 58 and the divided conductor 61 that are positioned are drawn out to the two side surfaces 12E and 12C that face each other, and the divided conductor 59 and the divided conductor 62 that are also positioned to face each other in the stacking direction. Are drawn out to the two side surfaces 12C and 12E facing each other.
Therefore, in the present embodiment, the divided conductors 58, 60, 62 are connected to the terminal electrode 33 shown in FIG. 2, respectively, and the divided conductors 57, 59, 61 are connected to the terminal electrode 34 shown in FIG. Will be.
[0049]
As described above, the current flows in the opposite direction between the split conductors 51, 52, 53 and the split conductors 54, 55, 56 as shown by the arrows in FIG. 7, and the split conductors 57, 58, 59 and the split conductors The current flows in the opposite direction between the arrows 60, 61, and 62 in the form shown by the arrows in FIG. Furthermore, the split conductors 51, 52, 53, the split conductors 54, 55, 56, the split conductors 57, 58, 59, and the split conductors 60, 61, 62 that extend side by side on the same plane, When current flows in the opposite direction between the adjacent divided conductors, an action of canceling out the magnetic field occurs.
[0050]
As a result, similar to the second embodiment, the parasitic inductance of the multilayer capacitor 10 itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0051]
Next, a fourth embodiment of the multilayer capacitor according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated in 1st Embodiment, and the overlapping description is abbreviate | omitted.
In the present embodiment, as shown in FIG. 8, the inner conductors 21 of the first embodiment are divided so as to extend side by side, and the two side surfaces 12B and 12D of the dielectric body 12 facing each other. A plurality of (two in this embodiment) divided conductors 71 and 72 are alternately drawn (shown in FIG. 2). However, in the present embodiment, the split conductor 71 is formed in a U-shape, and the split conductor 72 is formed in a T-shape, so that the split conductor 71 is split between the tip end portions extending in the left-right direction in FIG. The tip end portion of the conductor 72 is inserted.
[0052]
Also, the inner conductor 22 of the first embodiment is similarly divided into two extending side by side and alternately on the two side surfaces 12B and 12D of the dielectric element body 12 facing each other, and the reverse of the above A plurality (two in this embodiment) of divided conductors 73 and 74 are drawn out. However, in the present embodiment, the divided conductor 73 is formed in a U shape, and the divided conductor 74 is formed in a T shape, and the divided conductor 73 is divided between the distal end side portions extending in the left-right direction in FIG. The tip end portion of the conductor 74 is in a shape to enter.
[0053]
On the other hand, the inner conductor 23 of the first embodiment is also divided so as to extend side by side, and alternately drawn out to the two side surfaces 12C and 12E (shown in FIG. 2) of the dielectric element body 12 facing each other. A plurality (two in this embodiment) of divided conductors 75 and 76 are provided. However, in the present embodiment, the split conductor 75 is formed in a U-shape, and the split conductor 76 is formed in a T-shape. In addition, the tip end portion of the split conductor 76 is inserted.
[0054]
Similarly, the inner conductor 24 of the first embodiment is also divided into two extending side by side and alternately on the two side surfaces 12C and 12E facing each other of the dielectric element body 12, and the reverse of the above. A plurality of (two in this embodiment) divided conductors 77 and 78 are drawn out. However, in the present embodiment, the split conductor 77 is formed in a U-shape, and the split conductor 78 is formed in a T-shape. In addition, the tip end portion of the split conductor 78 is inserted.
[0055]
The divided conductors 71 and 74 are connected to the terminal electrode 31, the divided conductors 72 and 73 are connected to the terminal electrode 32, the divided conductors 75 and 78 are connected to the terminal electrode 33, and the divided conductors 76 and 77 are terminal electrodes. 34, the divided conductors 71 to 78 are respectively connected to the terminal electrodes 31 to 34 shown in FIG. 2 in the same manner as in the second embodiment.
[0056]
As described above, the current flows in the reverse direction as shown by the arrow in FIG. 8 between the split conductor 71 and the split conductor 73 positioned facing each other in the stacking direction, and the split conductor 72 and the split conductor 72 are similarly positioned. Similarly, the current flows in the opposite direction between the conductors 74, and the current is reversed in the form indicated by the arrows in FIG. 8 between the divided conductors 75 and 77 positioned opposite to each other in the stacking direction. When the current flows in the opposite direction and the current flows in the opposite direction between the split conductor 76 and the split conductor 78 positioned in the same manner, an action of canceling out the magnetic field is generated.
[0057]
Furthermore, since the T-shaped divided conductor 72 enters between the U-shaped divided conductors 71, the current flows in the opposite direction between the adjacent divided conductors 71, 72 extending side by side on the same plane. , Respectively, the action of canceling out the magnetic field occurs. In addition, even when the split conductors 73 and 74, the split conductors 75 and 76, and the split conductors 77 and 78 having the same structure are used in the reverse direction, an action of canceling out the magnetic field occurs.
[0058]
As a result, similar to the second embodiment, the parasitic inductance of the multilayer capacitor 10 itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0059]
Next, a fifth embodiment of the multilayer capacitor according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated in 1st Embodiment, and the overlapping description is abbreviate | omitted.
In the present embodiment, as shown in FIG. 9, the inner conductors 21 of the first embodiment are divided so as to extend side by side, and the two side surfaces 12B and 12D of the dielectric body 12 facing each other. A plurality (two in this embodiment) of divided conductors 81 and 82 are alternately drawn out (shown in FIG. 2). However, in the present embodiment, the divided conductor 81 and the divided conductor 82 are each formed in a substantially triangular shape.
[0060]
Also, the inner conductor 22 of the first embodiment is similarly divided into two extending side by side and alternately on the two side surfaces 12B and 12D of the dielectric element body 12 facing each other, and the reverse of the above A plurality (two in this embodiment) of divided conductors 83 and 84 are drawn out. However, in the present embodiment, the divided conductor 83 and the divided conductor 84 are each formed in a substantially triangular shape.
[0061]
On the other hand, the inner conductor 23 of the first embodiment is also divided so as to extend side by side, and alternately drawn out to the two side surfaces 12C and 12E (shown in FIG. 2) of the dielectric element body 12 facing each other. A plurality (two in this embodiment) of divided conductors 85 and 86 are provided. However, in this embodiment, the divided conductor 85 and the divided conductor 86 are each formed in a substantially triangular shape.
[0062]
Similarly, the inner conductor 24 of the first embodiment is also divided into two extending side by side and alternately on the two side surfaces 12C and 12E facing each other of the dielectric element body 12, and the reverse of the above. A plurality of (two in this embodiment) divided conductors 87 and 88 are drawn out. However, in the present embodiment, the divided conductor 87 and the divided conductor 88 are each formed in a substantially triangular shape.
[0063]
The divided conductors 81 and 84 are connected to the terminal electrode 31, the divided conductors 82 and 83 are connected to the terminal electrode 32, the divided conductors 85 and 88 are connected to the terminal electrode 33, and the divided conductors 86 and 87 are terminal electrodes. 34, the divided conductors 81 to 88 are connected to the terminal electrodes 31 to 34 shown in FIG. 2 in the same manner as in the second embodiment.
[0064]
As described above, the current flows in the reverse direction as shown by the arrows in FIG. 9 between the split conductor 81 and the split conductor 83 positioned facing each other in the stacking direction, and the split conductor 82 and the split conductor 82 are similarly positioned. Similarly, the current flows in the opposite direction between the conductors 84, and the current is reversed in the form indicated by the arrows in FIG. 9 between the divided conductors 85 and 87 positioned opposite to each other in the stacking direction. When the current flows in the opposite direction and the current flows in the opposite direction between the divided conductor 86 and the divided conductor 88 located in the same manner, an action of canceling out the magnetic fields is generated.
[0065]
Further, the currents flow in the opposite directions even in the adjacent split conductors 81 and 82, the split conductors 83 and 84, the split conductors 85 and 86, and the split conductors 87 and 88 extending side by side on the same plane. By flowing, an action of canceling out the magnetic fields is generated.
As a result, similar to the second embodiment, the parasitic inductance of the multilayer capacitor 10 itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0066]
Next, a sixth embodiment of the multilayer capacitor according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated in 1st Embodiment, and the overlapping description is abbreviate | omitted.
In the present embodiment, as shown in FIG. 10, the pair of first inner conductors are an inner conductor 91 and an inner conductor 92 that are formed in substantially the same manner as in the first embodiment. On the other hand, the pair of second inner conductors are divided into three divided conductors 57, 58, 59 and three divided conductors 60, 61, 62 formed in the same manner as in the third embodiment. .
[0067]
For this reason, in the present embodiment, the internal conductor 91 is connected to the terminal electrode 31, and the internal conductor 92 is connected to the terminal electrode 32. Further, the divided conductors 58, 60, and 62 are connected to the terminal electrode 33, respectively, and the divided conductors 57, 59, and 61 are connected to the terminal electrode 34, respectively.
[0068]
From the above, between the inner conductor 91 and the inner conductor 92 positioned facing each other in the stacking direction, a current flows in the reverse direction as indicated by the arrow in FIG. 58, 59 and the split conductors 60, 61, 62 similarly cause currents to flow in opposite directions, thereby not only canceling the magnetic field, but also split conductors extending side by side on the same plane. Even between 57, 58, 59 and between the divided conductors 60, 61, 62, the current flows in the opposite direction between the adjacent divided conductors, thereby causing an action of canceling out the magnetic field.
[0069]
As a result, similar to the second embodiment, the parasitic inductance of the multilayer capacitor 10 itself can be further reduced, and the effect of reducing the equivalent series inductance is increased.
[0070]
Next, using a network analyzer, S21 characteristics of S parameters of the following samples were measured, and attenuation characteristics of the samples were obtained. First, the content of each sample will be described. That is, a general two-terminal multilayer capacitor shown in FIGS. 16 and 17 is used as a conventional capacitor, and a four-terminal multilayer capacitor according to the second embodiment shown in FIGS. 5 and 6 is used as an example. Then, this conventional example was connected to Port 1 and Port 2 of the network analyzer as shown in FIG. 11A, and this example was also connected as shown in FIG.
[0071]
Here, the constant of the equivalent circuit was calculated so that the measured value of the attenuation characteristic and the attenuation amount of the equivalent circuit shown in FIG. Then, it can be seen from the attenuation characteristic data of each sample shown in FIG. 12 that the attenuation amount of the example in the high frequency band of 20 MHz or more is increased by about 15 dB compared to the conventional example. For this reason, it can be understood that the improvement of the high-frequency characteristics can be seen in the examples by this data.
On the other hand, with respect to the ESL calculated and shown in Table 1, the examples were significantly reduced compared to the conventional example, and it was confirmed that the effects of the present invention were also demonstrated by Table 1.
[0072]
[Table 1]

[0073]
In Table 1, C is a capacitance, and ESR is an equivalent series resistance. As shown in FIGS. 16 and 2, the dimension of each sample used here is a distance L between the side surfaces of the dielectric body from which the pair of inner conductors are drawn, and the pair of inner conductors. When the distance between the side surfaces orthogonal to the side surface of the dielectric body from which the wire is drawn is a dimension W, the conventional example is L = 2.0 mm and W = l. It was 25 mm. In the example, L = 1.6 mm and W = 1.6 mm.
[0074]
In the multilayer capacitor 10 according to the above-described embodiment, the structure has a total of eight layers of four layers, but the number of layers is not limited to these numbers, and the number of layers may be increased. For example, it may be tens or hundreds. Further, in the second and subsequent embodiments, the structure in which two or three divided conductors are arranged is shown, but four or more of these divided conductors are arranged. You may make it do.
[0075]
【The invention's effect】
According to the present invention, it is possible to provide a multilayer capacitor with significantly reduced ESL.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a multilayer capacitor in accordance with a first embodiment of the present invention.
FIG. 2 is a perspective view showing the multilayer capacitor in accordance with the first embodiment of the present invention.
3 is a cross-sectional view showing the multilayer capacitor in accordance with the first embodiment of the present invention, and corresponds to a cross section taken along line 3-3 in FIG.
FIG. 4 is an equivalent circuit diagram of the multilayer capacitor in accordance with the first embodiment of the present invention.
FIG. 5 is an exploded perspective view of the multilayer capacitor in accordance with a second embodiment of the present invention.
6 is a cross-sectional view showing the multilayer capacitor in accordance with the second embodiment of the present invention, and corresponds to a cross section taken along line 3-3 in FIG. 2;
FIG. 7 is an exploded perspective view of the multilayer capacitor in accordance with a third embodiment of the present invention.
FIG. 8 is an exploded perspective view of the multilayer capacitor in accordance with a fourth embodiment of the present invention.
FIG. 9 is an exploded perspective view of the multilayer capacitor in accordance with a fifth embodiment of the present invention.
FIG. 10 is an exploded perspective view of a multilayer capacitor in accordance with a sixth embodiment of the present invention.
11A and 11B are circuit diagrams showing connection of each sample to a network analyzer, where FIG. 11A is a diagram showing connection in a conventional example, and FIG. 11B is a diagram showing connection in an example.
FIG. 12 is a graph showing attenuation characteristics of each sample.
FIG. 13 is a circuit diagram employing a conventional multilayer capacitor.
FIG. 14 is a graph showing a relationship between current fluctuation and voltage fluctuation in a circuit employing a multilayer capacitor of a conventional example.
FIG. 15 is an equivalent circuit diagram of a multilayer capacitor according to a conventional example.
FIG. 16 is a perspective view showing a multilayer capacitor according to a conventional example.
FIG. 17 is an exploded perspective view showing an internal conductor portion of a multilayer capacitor according to a conventional example.
[Explanation of symbols]
10 multilayer capacitors
12 Dielectric body
12B side
12C side
12D side
12E side
21, 22 Internal electrode (first internal conductor)
23, 24 Internal electrode (second internal conductor)
31, 32 terminal electrode (first terminal electrode)
33, 34 Terminal electrode (second terminal electrode)
41 to 44 Split conductor (first inner conductor)
45 to 48 Split conductor (second inner conductor)
51-56 Split conductor (first inner conductor)
57 to 62 Split conductor (second inner conductor)
71-74 Split conductor (first inner conductor)
75 to 78 Split conductor (second inner conductor)
81-84 Split conductor (first inner conductor)
85 to 88 Split conductor (second inner conductor)
91, 92 Internal electrode (first internal conductor)

Claims (3)

A multilayer capacitor in which a plurality of internal conductors are respectively disposed in a form sandwiched between dielectric sheets in a dielectric body formed by laminating a plurality of dielectric sheets,
A pair of first inner conductor their respective issued can pull in two sides facing each other of the dielectric body,
A pair of second inner conductor pair of the first inner conductor is issued come second side thereto respectively argument to be opposed to each other of the two sides with different dielectric body drawn,
The above-mentioned plurality of inner conductors are configured,
Any one of the other inner conductors is disposed between one inner conductor of the pair of first inner conductors and the pair of second inner conductors ,
At least one of the pair of first inner conductors or the pair of second inner conductors is linearly extended alongside each other, and is divided so as to be opposed to each other in the stacking direction. The multilayer capacitor is a plurality of divided conductors that are alternately protruded from two opposite sides of the element body ,
A pair of first terminal electrodes are disposed respectively in two sides facing each other of the dielectric body to be and connected pair of first internal conductor Niso respectively,
A pair of second terminal electrodes which are arranged and connected pair of second inner conductor Niso respectively each in two sides facing each other of the two sides with different dielectric body in which the first terminal electrode is arranged,
A multilayer capacitor comprising: The multilayer capacitor according to claim 1, wherein the dielectric body is formed in a rectangular parallelepiped shape . 3. The multilayer capacitor according to claim 1 , wherein a plurality of pairs of first inner conductors and second inner conductors are arranged in the dielectric body .

Images