HK1036861A1 - A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state. - Google Patents
A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state.Info
- Publication number
- HK1036861A1 HK1036861A1 HK01107756A HK01107756A HK1036861A1 HK 1036861 A1 HK1036861 A1 HK 1036861A1 HK 01107756 A HK01107756 A HK 01107756A HK 01107756 A HK01107756 A HK 01107756A HK 1036861 A1 HK1036861 A1 HK 1036861A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- self
- random access
- access memory
- low power
- dynamic random
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/167,507 US6112306A (en) | 1998-10-06 | 1998-10-06 | Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state |
PCT/US1999/023168 WO2000020954A1 (en) | 1998-10-06 | 1999-10-04 | A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1036861A1 true HK1036861A1 (en) | 2002-01-18 |
Family
ID=22607647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK01107756A HK1036861A1 (en) | 1998-10-06 | 2001-11-06 | A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state. |
Country Status (7)
Country | Link |
---|---|
US (1) | US6112306A (xx) |
EP (1) | EP1127306B1 (xx) |
KR (1) | KR100432700B1 (xx) |
AU (1) | AU1102200A (xx) |
DE (1) | DE69922830T2 (xx) |
HK (1) | HK1036861A1 (xx) |
WO (1) | WO2000020954A1 (xx) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6457095B1 (en) * | 1999-12-13 | 2002-09-24 | Intel Corporation | Method and apparatus for synchronizing dynamic random access memory exiting from a low power state |
US6886105B2 (en) * | 2000-02-14 | 2005-04-26 | Intel Corporation | Method and apparatus for resuming memory operations from a low latency wake-up low power state |
US6996235B2 (en) | 2001-10-08 | 2006-02-07 | Pitney Bowes Inc. | Method and system for secure printing of documents via a printer coupled to the internet |
US7000133B2 (en) * | 2002-03-22 | 2006-02-14 | Intel Corporation | Method and apparatus for controlling power states in a memory device utilizing state information |
FI20021867A (fi) * | 2002-10-18 | 2004-04-19 | Nokia Corp | Menetelmä kortin toimintatilan muuttamiseksi, järjestelmä, kortti ja laite |
JP2007200504A (ja) | 2006-01-30 | 2007-08-09 | Fujitsu Ltd | 半導体メモリ、メモリコントローラ及び半導体メモリの制御方法 |
US7466174B2 (en) | 2006-03-31 | 2008-12-16 | Intel Corporation | Fast lock scheme for phase locked loops and delay locked loops |
EP2102754B1 (en) * | 2006-12-20 | 2013-03-20 | Nxp B.V. | Clock generation for memory access without a local oscillator |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8801472D0 (en) * | 1988-01-22 | 1988-02-24 | Int Computers Ltd | Dynamic random-access memory |
JP2697412B2 (ja) * | 1991-10-25 | 1998-01-14 | 日本電気株式会社 | ダイナミックram |
US5365487A (en) * | 1992-03-24 | 1994-11-15 | Texas Instruments Incorporated | DRAM power management with self-refresh |
US5337285A (en) * | 1993-05-21 | 1994-08-09 | Rambus, Inc. | Method and apparatus for power control in devices |
US5638083A (en) * | 1993-07-07 | 1997-06-10 | Chips And Technologies, Inc. | System for allowing synchronous sleep mode operation within a computer |
JPH07129287A (ja) * | 1993-11-01 | 1995-05-19 | Canon Inc | コンピュータ装置 |
JP3489906B2 (ja) * | 1995-04-18 | 2004-01-26 | 松下電器産業株式会社 | 半導体メモリ装置 |
US6067649A (en) * | 1998-06-10 | 2000-05-23 | Compaq Computer Corporation | Method and apparatus for a low power self test of a memory subsystem |
-
1998
- 1998-10-06 US US09/167,507 patent/US6112306A/en not_active Expired - Lifetime
-
1999
- 1999-10-04 KR KR10-2001-7004305A patent/KR100432700B1/ko not_active IP Right Cessation
- 1999-10-04 DE DE69922830T patent/DE69922830T2/de not_active Expired - Lifetime
- 1999-10-04 EP EP99954743A patent/EP1127306B1/en not_active Expired - Lifetime
- 1999-10-04 WO PCT/US1999/023168 patent/WO2000020954A1/en active IP Right Grant
- 1999-10-04 AU AU11022/00A patent/AU1102200A/en not_active Abandoned
-
2001
- 2001-11-06 HK HK01107756A patent/HK1036861A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1127306A4 (en) | 2003-03-05 |
AU1102200A (en) | 2000-04-26 |
KR20020008107A (ko) | 2002-01-29 |
WO2000020954A1 (en) | 2000-04-13 |
EP1127306B1 (en) | 2004-12-22 |
US6112306A (en) | 2000-08-29 |
DE69922830T2 (de) | 2005-12-15 |
DE69922830D1 (de) | 2005-01-27 |
KR100432700B1 (ko) | 2004-05-24 |
EP1127306A1 (en) | 2001-08-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU2916001A (en) | Method and apparatus for synchronizing dynamic random access memory exiting froma low power state | |
GB2381622B (en) | Synchronous dynamic random access memory apparatus | |
HK1035255A1 (en) | Method and apparatus for a serial access memory. | |
GB2310745B (en) | Dynamic random access memory | |
EP0706186A3 (en) | DRAM memory devices | |
AU4307999A (en) | Method and system for providing a random number generator | |
EP1004119A4 (en) | DRAM MEMORY SYSTEM WITH SIMULTANEOUS ACCESS AND REGENERATION OPERATIONS AND METHODS OF USE | |
HK1038091A1 (en) | Method and apparatus for implementing dynamic display memory | |
SG53006A1 (en) | Dynamic memory device with refresh circuit and refresh method | |
EP0646928A3 (en) | Dynamic synchronous random access memory. | |
AU4678900A (en) | Method and apparatus for random noise generator | |
TW542395U (en) | Multilevel memory access method apparatus | |
EP0973097A4 (en) | MEMORY AND METHOD FOR ACCESSING THE MEMORY | |
GB2311153B (en) | Random access memories and method of operation | |
IL112737A0 (en) | Method and apparatus for controlling dynamic random access memory devices | |
GB0030187D0 (en) | Selective storage access method and apparatus | |
AU1525300A (en) | Method and apparatus for hardening a static random access memory cell from single event upsets | |
HK1036861A1 (en) | A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state. | |
HUP0003983A2 (en) | Method and device for generating a variable spindle rotation, and direct access storage device | |
AU2001290996A1 (en) | Method and apparatus for generating massive interrupts in random access memory (ram) | |
GB9727213D0 (en) | Method of fabricating a dynamic random access memory device | |
GB9801492D0 (en) | Random number generation method and apparatus | |
GB9915341D0 (en) | Multiple access parallel memory and method | |
HK1019252A1 (en) | Storage device and access method. | |
TW488556U (en) | Memory package method and apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |
Effective date: 20101004 |