HK1036861A1 - A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state. - Google Patents

A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state.

Info

Publication number
HK1036861A1
HK1036861A1 HK01107756A HK01107756A HK1036861A1 HK 1036861 A1 HK1036861 A1 HK 1036861A1 HK 01107756 A HK01107756 A HK 01107756A HK 01107756 A HK01107756 A HK 01107756A HK 1036861 A1 HK1036861 A1 HK 1036861A1
Authority
HK
Hong Kong
Prior art keywords
self
random access
access memory
low power
dynamic random
Prior art date
Application number
HK01107756A
Other languages
English (en)
Inventor
Andrew M Volk
Michael W Williams
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1036861A1 publication Critical patent/HK1036861A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
HK01107756A 1998-10-06 2001-11-06 A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state. HK1036861A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/167,507 US6112306A (en) 1998-10-06 1998-10-06 Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state
PCT/US1999/023168 WO2000020954A1 (en) 1998-10-06 1999-10-04 A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state

Publications (1)

Publication Number Publication Date
HK1036861A1 true HK1036861A1 (en) 2002-01-18

Family

ID=22607647

Family Applications (1)

Application Number Title Priority Date Filing Date
HK01107756A HK1036861A1 (en) 1998-10-06 2001-11-06 A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state.

Country Status (7)

Country Link
US (1) US6112306A (xx)
EP (1) EP1127306B1 (xx)
KR (1) KR100432700B1 (xx)
AU (1) AU1102200A (xx)
DE (1) DE69922830T2 (xx)
HK (1) HK1036861A1 (xx)
WO (1) WO2000020954A1 (xx)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6457095B1 (en) * 1999-12-13 2002-09-24 Intel Corporation Method and apparatus for synchronizing dynamic random access memory exiting from a low power state
US6886105B2 (en) * 2000-02-14 2005-04-26 Intel Corporation Method and apparatus for resuming memory operations from a low latency wake-up low power state
US6996235B2 (en) 2001-10-08 2006-02-07 Pitney Bowes Inc. Method and system for secure printing of documents via a printer coupled to the internet
US7000133B2 (en) * 2002-03-22 2006-02-14 Intel Corporation Method and apparatus for controlling power states in a memory device utilizing state information
FI20021867A (fi) * 2002-10-18 2004-04-19 Nokia Corp Menetelmä kortin toimintatilan muuttamiseksi, järjestelmä, kortti ja laite
JP2007200504A (ja) 2006-01-30 2007-08-09 Fujitsu Ltd 半導体メモリ、メモリコントローラ及び半導体メモリの制御方法
US7466174B2 (en) 2006-03-31 2008-12-16 Intel Corporation Fast lock scheme for phase locked loops and delay locked loops
EP2102754B1 (en) * 2006-12-20 2013-03-20 Nxp B.V. Clock generation for memory access without a local oscillator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8801472D0 (en) * 1988-01-22 1988-02-24 Int Computers Ltd Dynamic random-access memory
JP2697412B2 (ja) * 1991-10-25 1998-01-14 日本電気株式会社 ダイナミックｒａｍ
US5365487A (en) * 1992-03-24 1994-11-15 Texas Instruments Incorporated DRAM power management with self-refresh
US5337285A (en) * 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices
US5638083A (en) * 1993-07-07 1997-06-10 Chips And Technologies, Inc. System for allowing synchronous sleep mode operation within a computer
JPH07129287A (ja) * 1993-11-01 1995-05-19 Canon Inc コンピュータ装置
JP3489906B2 (ja) * 1995-04-18 2004-01-26 松下電器産業株式会社 半導体メモリ装置
US6067649A (en) * 1998-06-10 2000-05-23 Compaq Computer Corporation Method and apparatus for a low power self test of a memory subsystem

Also Published As

Publication number Publication date
WO2000020954A1 (en) 2000-04-13
EP1127306B1 (en) 2004-12-22
EP1127306A4 (en) 2003-03-05
KR20020008107A (ko) 2002-01-29
DE69922830T2 (de) 2005-12-15
KR100432700B1 (ko) 2004-05-24
EP1127306A1 (en) 2001-08-29
US6112306A (en) 2000-08-29
AU1102200A (en) 2000-04-26
DE69922830D1 (de) 2005-01-27

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20101004