AU2001290996A1 - Method and apparatus for generating massive interrupts in random access memory (ram) - Google Patents

Method and apparatus for generating massive interrupts in random access memory (ram)

Info

Publication number
AU2001290996A1
AU2001290996A1 AU2001290996A AU9099601A AU2001290996A1 AU 2001290996 A1 AU2001290996 A1 AU 2001290996A1 AU 2001290996 A AU2001290996 A AU 2001290996A AU 9099601 A AU9099601 A AU 9099601A AU 2001290996 A1 AU2001290996 A1 AU 2001290996A1
Authority
AU
Australia
Prior art keywords
interrupts
ram
random access
access memory
generating massive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001290996A
Inventor
Sandra Maria Frazier
Ben-Zur Raanan
Shi-Woang Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ciena Corp
Original Assignee
Ciena Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ciena Corp filed Critical Ciena Corp
Publication of AU2001290996A1 publication Critical patent/AU2001290996A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13058—Interrupt request
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103—Memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13174—Data transmission, file transfer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13178—Control signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13216—Code signals, frame structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
AU2001290996A 2000-09-15 2001-09-14 Method and apparatus for generating massive interrupts in random access memory (ram) Abandoned AU2001290996A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/663,260 2000-09-15
US09/663,260 US6633573B1 (en) 2000-09-15 2000-09-15 Method and apparatus for generating massive interrupts in random access memory (RAM)
PCT/US2001/028918 WO2002023942A2 (en) 2000-09-15 2001-09-14 Method and apparatus for generating massive interrupts in random access memory (ram)

Publications (1)

Publication Number Publication Date
AU2001290996A1 true AU2001290996A1 (en) 2002-03-26

Family

ID=24661071

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001290996A Abandoned AU2001290996A1 (en) 2000-09-15 2001-09-14 Method and apparatus for generating massive interrupts in random access memory (ram)

Country Status (3)

Country Link
US (1) US6633573B1 (en)
AU (1) AU2001290996A1 (en)
WO (1) WO2002023942A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352758B2 (en) * 2000-02-18 2008-04-01 Tellabs Operations, Inc. Dynamic bandwidth management using signaling protocol and virtual concatenation
US6920105B1 (en) * 2000-09-15 2005-07-19 Ciena Corporation Interface receive for communications among network elements
US6754174B1 (en) * 2000-09-15 2004-06-22 Ciena Corporation Interface for communications among network elements
US6785766B1 (en) * 2000-09-15 2004-08-31 Ciena Corporation Method and apparatus for servicing massive interrupts in random access memory (RAM)
US6865148B1 (en) * 2000-09-15 2005-03-08 Ciena Corporation Method for routing network switching information
US7054324B1 (en) * 2000-09-15 2006-05-30 Ciena Corporation Interface transmitter for communications among network elements
US7640359B1 (en) 2003-09-19 2009-12-29 At&T Intellectual Property, I, L.P. Method, system and computer program product for facilitating the design and assignment of ethernet VLANs
US7624187B1 (en) 2003-09-19 2009-11-24 At&T Intellectual Property, I, L.P. Method, system and computer program product for providing Ethernet VLAN capacity requirement estimation
US20050066036A1 (en) * 2003-09-19 2005-03-24 Neil Gilmartin Methods, systems and computer program products for facilitating the design and analysis of virtual networks based on total hub value
US7958208B2 (en) * 2004-09-22 2011-06-07 At&T Intellectual Property I, L.P. System and method for designing a customized switched metro Ethernet data network
CN100432946C (en) * 2005-12-31 2008-11-12 华为技术有限公司 Device and method for implementing protection switching control

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313582A (en) * 1991-04-30 1994-05-17 Standard Microsystems Corporation Method and apparatus for buffering data within stations of a communication network
US5341364A (en) 1992-06-02 1994-08-23 At&T Bell Laboratories Distributed switching in bidirectional multiplex section-switched ringtransmission systems
US5784377A (en) 1993-03-09 1998-07-21 Hubbell Incorporated Integrated digital loop carrier system with virtual tributary mapper circuit
US5619642A (en) * 1994-12-23 1997-04-08 Emc Corporation Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device
US6275680B1 (en) * 1997-07-29 2001-08-14 Philips Semiconductors, Inc. Hardware PCH checking for personal handyphone system portable station
US6105079A (en) * 1997-12-18 2000-08-15 Advanced Micro Devices, Inc. Apparatus and method in a network interface device for selectively supplying long bit information related to a data frame to a buffer memory and a read controller for initiation of data transfers

Also Published As

Publication number Publication date
US6633573B1 (en) 2003-10-14
WO2002023942A2 (en) 2002-03-21
WO2002023942A3 (en) 2003-01-09

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