HK1007366B - 宽频带数字相位校准器 - Google Patents

宽频带数字相位校准器 Download PDF

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Publication number
HK1007366B
HK1007366B HK98106539.8A HK98106539A HK1007366B HK 1007366 B HK1007366 B HK 1007366B HK 98106539 A HK98106539 A HK 98106539A HK 1007366 B HK1007366 B HK 1007366B
Authority
HK
Hong Kong
Prior art keywords
data
register
phase
output
registers
Prior art date
Application number
HK98106539.8A
Other languages
German (de)
English (en)
French (fr)
Other versions
HK1007366A1 (zh
Inventor
W. Lowrey Scott
A. Porter Jeffrey
Original Assignee
General Dynamics Decision Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Dynamics Decision Systems, Inc. filed Critical General Dynamics Decision Systems, Inc.
Publication of HK1007366B publication Critical patent/HK1007366B/zh
Publication of HK1007366A1 publication Critical patent/HK1007366A1/zh

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HK98106539A 1991-05-01 1998-06-25 宽频带数字相位校准器 HK1007366A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69417591A 1991-05-01 1991-05-01
US694175 1991-05-01

Publications (2)

Publication Number Publication Date
HK1007366B true HK1007366B (zh) 1999-04-09
HK1007366A1 HK1007366A1 (zh) 1999-04-09

Family

ID=24787717

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98106539A HK1007366A1 (zh) 1991-05-01 1998-06-25 宽频带数字相位校准器

Country Status (5)

Country Link
US (1) US5278873A (zh)
EP (1) EP0511836B1 (zh)
JP (1) JPH05191225A (zh)
DE (1) DE69218999T2 (zh)
HK (1) HK1007366A1 (zh)

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US5487095A (en) * 1994-06-17 1996-01-23 International Business Machines Corporation Edge detector
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US5828257A (en) * 1995-09-08 1998-10-27 International Business Machines Corporation Precision time interval division with digital phase delay lines
US5675273A (en) * 1995-09-08 1997-10-07 International Business Machines Corporation Clock regulator with precision midcycle edge timing
US5608357A (en) * 1995-09-12 1997-03-04 Vlsi Technology, Inc. High speed phase aligner with jitter removal
US5905769A (en) * 1996-05-07 1999-05-18 Silicon Image, Inc. System and method for high-speed skew-insensitive multi-channel data transmission
US5831459A (en) * 1995-11-13 1998-11-03 International Business Machines Corporation Method and system for adjusting a clock signal within electronic circuitry
KR0153952B1 (ko) * 1995-12-16 1998-11-16 양승택 고속 디지털 데이터 리타이밍 장치
US5748020A (en) * 1996-02-02 1998-05-05 Lsi Logic Corporation High speed capture latch
US5694062A (en) * 1996-02-02 1997-12-02 Lsi Logic Corporation Self-timed phase detector and method
US5633899A (en) * 1996-02-02 1997-05-27 Lsi Logic Corporation Phase locked loop for high speed data capture of a serial data stream
US5692166A (en) * 1996-04-19 1997-11-25 Motorola, Inc. Method and system for resynchronizing a phase-shifted received data stream with a master clock
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US6182237B1 (en) 1998-08-31 2001-01-30 International Business Machines Corporation System and method for detecting phase errors in asics with multiple clock frequencies
US6466626B1 (en) 1999-02-23 2002-10-15 International Business Machines Corporation Driver with in-situ variable compensation for cable attenuation
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US7418068B2 (en) * 2001-02-24 2008-08-26 International Business Machines Corporation Data capture technique for high speed signaling
US20020170591A1 (en) * 2001-05-15 2002-11-21 Pharmaseq, Inc. Method and apparatus for powering circuitry with on-chip solar cells within a common substrate
US20030061564A1 (en) * 2001-09-27 2003-03-27 Maddux John T. Serial data extraction using two cycles of edge information
US7092466B2 (en) * 2001-12-17 2006-08-15 Broadcom Corporation System and method for recovering and deserializing a high data rate bit stream
US6690201B1 (en) * 2002-01-28 2004-02-10 Xilinx, Inc. Method and apparatus for locating data transition regions
US7099416B2 (en) * 2002-02-06 2006-08-29 Broadcom Corporation Single ended termination of clock for dual link DVI receiver
US7308059B2 (en) * 2002-02-06 2007-12-11 Broadcom Corporation Synchronization of data links in a multiple link receiver
US7120203B2 (en) * 2002-02-12 2006-10-10 Broadcom Corporation Dual link DVI transmitter serviced by single Phase Locked Loop
JP2003333110A (ja) * 2002-05-17 2003-11-21 Mitsubishi Electric Corp シリアルデータ受信回路
US7034597B1 (en) 2004-09-03 2006-04-25 Ami Semiconductor, Inc. Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
US7433442B2 (en) * 2004-09-23 2008-10-07 Standard Microsystems Corporation Linear half-rate clock and data recovery (CDR) circuit
TW200710632A (en) * 2005-09-09 2007-03-16 Via Tech Inc Timing adjustment circuit and method
US20070058766A1 (en) * 2005-09-14 2007-03-15 Tellabs Operations, Inc. Methods and apparatus for recovering serial data
EP1798887B1 (en) * 2005-12-16 2010-04-21 STMicroelectronics (Research & Development) Limited Isochronous synchronizer
US7863931B1 (en) * 2007-11-14 2011-01-04 Lattice Semiconductor Corporation Flexible delay cell architecture
US7768325B2 (en) * 2008-04-23 2010-08-03 International Business Machines Corporation Circuit and design structure for synchronizing multiple digital signals
US20160080138A1 (en) * 2014-09-17 2016-03-17 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for timing synchronization in a distributed timing system

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FR2567696B1 (fr) * 1984-07-13 1991-06-28 Thomas Alain Dispositif de cadrage automatique d'horloge locale par rapport a un signal de donnees et circuit d'echantillonnage en comportant application
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US4841551A (en) * 1987-01-05 1989-06-20 Grumman Aerospace Corporation High speed data-clock synchronization processor
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US4839907A (en) * 1988-02-26 1989-06-13 American Telephone And Telegraph Company, At&T Bell Laboratories Clock skew correction arrangement
US4949361A (en) * 1989-06-26 1990-08-14 Tektronix, Inc. Digital data transfer synchronization circuit and method

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