HK1003155A1 - An apparatus and method for increasing the burst rate of edo drams in a computer system - Google Patents

An apparatus and method for increasing the burst rate of edo drams in a computer system

Info

Publication number
HK1003155A1
HK1003155A1 HK98101970A HK98101970A HK1003155A1 HK 1003155 A1 HK1003155 A1 HK 1003155A1 HK 98101970 A HK98101970 A HK 98101970A HK 98101970 A HK98101970 A HK 98101970A HK 1003155 A1 HK1003155 A1 HK 1003155A1
Authority
HK
Hong Kong
Prior art keywords
increasing
computer system
burst rate
edo drams
edo
Prior art date
Application number
HK98101970A
Other languages
English (en)
Inventor
George R Hayek
Joe M Nardone
Aniruddha Kundu
Kuljit S Bains
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1003155A1 publication Critical patent/HK1003155A1/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
HK98101970A 1994-12-30 1998-03-10 An apparatus and method for increasing the burst rate of edo drams in a computer system HK1003155A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/367,807 US6112284A (en) 1994-12-30 1994-12-30 Method and apparatus for latching data from a memory resource at a datapath unit
PCT/US1995/016880 WO1996021226A1 (en) 1994-12-30 1995-12-28 An apparatus and method for increasing the burst rate of edo drams in a computer system

Publications (1)

Publication Number Publication Date
HK1003155A1 true HK1003155A1 (en) 1998-10-16

Family

ID=23448696

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98101970A HK1003155A1 (en) 1994-12-30 1998-03-10 An apparatus and method for increasing the burst rate of edo drams in a computer system

Country Status (7)

Country Link
US (1) US6112284A (ko)
KR (1) KR100300154B1 (ko)
AU (1) AU4742796A (ko)
DE (1) DE19581689B4 (ko)
GB (1) GB2310938B (ko)
HK (1) HK1003155A1 (ko)
WO (1) WO1996021226A1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
KR100496787B1 (ko) * 1997-08-08 2005-09-12 삼성전자주식회사 고속반도체메모리장치의억세스시간을줄이기위한제어방법및컨트롤라
US6557071B2 (en) * 1998-06-22 2003-04-29 Intel Corporation Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage
US6691214B1 (en) * 2000-08-29 2004-02-10 Micron Technology, Inc. DDR II write data capture calibration
US6658604B1 (en) * 2000-10-10 2003-12-02 International Business Machines Corporation Method for testing and guaranteeing that skew between two signals meets predetermined criteria
US6456544B1 (en) * 2001-03-30 2002-09-24 Intel Corporation Selective forwarding of a strobe based on a predetermined delay following a memory read command
US6512704B1 (en) 2001-09-14 2003-01-28 Sun Microsystems, Inc. Data strobe receiver
US6889334B1 (en) * 2001-10-02 2005-05-03 Advanced Micro Devices, Inc. Multimode system for calibrating a data strobe delay for a memory read operation
US7076678B2 (en) * 2002-02-11 2006-07-11 Micron Technology, Inc. Method and apparatus for data transfer

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117492A (ja) * 1983-11-29 1985-06-24 Fujitsu Ltd 半導体記憶装置
US4792929A (en) * 1987-03-23 1988-12-20 Zenith Electronics Corporation Data processing system with extended memory access
US4953130A (en) * 1988-06-27 1990-08-28 Texas Instruments, Incorporated Memory circuit with extended valid data output time
JP2555900B2 (ja) * 1990-02-06 1996-11-20 日本電気株式会社 半導体メモリの出力制御回路
US5036230A (en) * 1990-03-01 1991-07-30 Intel Corporation CMOS clock-phase synthesizer
US5341488A (en) * 1990-04-11 1994-08-23 Nec Electronics, Inc. N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus
JP2977296B2 (ja) * 1991-02-19 1999-11-15 沖電気工業株式会社 半導体メモリ装置
US5278803A (en) * 1991-09-11 1994-01-11 Compaq Computer Corporation Memory column address strobe buffer and synchronization and data latch interlock
JP3097301B2 (ja) * 1992-04-28 2000-10-10 日本電気株式会社 半導体メモリ装置
EP0607668B1 (en) * 1993-01-21 1999-03-03 Advanced Micro Devices, Inc. Electronic memory system and method
JPH07192470A (ja) * 1993-03-08 1995-07-28 Nec Ic Microcomput Syst Ltd 半導体メモリの出力回路
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data
US5511152A (en) * 1993-09-20 1996-04-23 Digital Equipment Corporation Memory subsystem for bitmap printer data controller
US5488581A (en) * 1993-10-28 1996-01-30 Fujitsu Limited Semiconductor memory device
US5457659A (en) * 1994-07-19 1995-10-10 Micron Technology, Inc. Programmable dynamic random access memory (DRAM)
US5490114A (en) * 1994-12-22 1996-02-06 International Business Machines Corporation High performance extended data out
US5598376A (en) * 1994-12-23 1997-01-28 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5546344A (en) * 1995-06-06 1996-08-13 Cirrus Logic, Inc. Extended data output DRAM interface
US5555209A (en) * 1995-08-02 1996-09-10 Simple Technology, Inc. Circuit for latching data signals from DRAM memory
US5568430A (en) * 1995-12-04 1996-10-22 Etron Technology, Inc. Self timed address locking and data latching circuit

Also Published As

Publication number Publication date
GB9626481D0 (en) 1997-02-05
US6112284A (en) 2000-08-29
WO1996021226A1 (en) 1996-07-11
KR100300154B1 (ko) 2001-10-27
DE19581689B4 (de) 2007-11-22
AU4742796A (en) 1996-07-24
DE19581689T1 (de) 1997-06-05
GB2310938A (en) 1997-09-10
GB2310938B (en) 2000-03-22
KR970705141A (ko) 1997-09-06

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20101228