GB9726477D0 - Binary adder - Google Patents

Binary adder

Info

Publication number
GB9726477D0
GB9726477D0 GBGB9726477.4A GB9726477A GB9726477D0 GB 9726477 D0 GB9726477 D0 GB 9726477D0 GB 9726477 A GB9726477 A GB 9726477A GB 9726477 D0 GB9726477 D0 GB 9726477D0
Authority
GB
United Kingdom
Prior art keywords
binary adder
adder
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB9726477.4A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Priority to GBGB9726477.4A priority Critical patent/GB9726477D0/en
Publication of GB9726477D0 publication Critical patent/GB9726477D0/en
Priority to DE69817614T priority patent/DE69817614T2/de
Priority to AU14948/99A priority patent/AU1494899A/en
Priority to CA002313241A priority patent/CA2313241C/en
Priority to EP98959009A priority patent/EP1038208B1/en
Priority to JP2000539394A priority patent/JP4481490B2/ja
Priority to US09/555,768 priority patent/US6711604B1/en
Priority to PCT/GB1998/003655 priority patent/WO1999031562A2/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E1/00—Devices for processing exclusively digital data
    • G06E1/02—Devices for processing exclusively digital data operating upon the order or content of the data handled
    • G06E1/04—Devices for processing exclusively digital data operating upon the order or content of the data handled for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Optical Communication System (AREA)
  • Image Analysis (AREA)
GBGB9726477.4A 1997-12-15 1997-12-15 Binary adder Ceased GB9726477D0 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
GBGB9726477.4A GB9726477D0 (en) 1997-12-15 1997-12-15 Binary adder
DE69817614T DE69817614T2 (de) 1997-12-15 1998-12-08 Binär addierer
AU14948/99A AU1494899A (en) 1997-12-15 1998-12-08 Binary adder
CA002313241A CA2313241C (en) 1997-12-15 1998-12-08 Binary adder
EP98959009A EP1038208B1 (en) 1997-12-15 1998-12-08 Binary adder
JP2000539394A JP4481490B2 (ja) 1997-12-15 1998-12-08 二値加算器
US09/555,768 US6711604B1 (en) 1997-12-15 1998-12-08 Binary adder
PCT/GB1998/003655 WO1999031562A2 (en) 1997-12-15 1998-12-08 Binary adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9726477.4A GB9726477D0 (en) 1997-12-15 1997-12-15 Binary adder

Publications (1)

Publication Number Publication Date
GB9726477D0 true GB9726477D0 (en) 1998-02-11

Family

ID=10823636

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB9726477.4A Ceased GB9726477D0 (en) 1997-12-15 1997-12-15 Binary adder

Country Status (8)

Country Link
US (1) US6711604B1 (enExample)
EP (1) EP1038208B1 (enExample)
JP (1) JP4481490B2 (enExample)
AU (1) AU1494899A (enExample)
CA (1) CA2313241C (enExample)
DE (1) DE69817614T2 (enExample)
GB (1) GB9726477D0 (enExample)
WO (1) WO1999031562A2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2533078C1 (ru) * 2013-07-09 2014-11-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" Двоичный сумматор

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61138337A (ja) * 1984-12-10 1986-06-25 Matsushita Electric Ind Co Ltd 計数回路
GB2201534A (en) * 1987-02-19 1988-09-01 British Telecomm Arithmetic assembly
JP3182143B2 (ja) * 1989-06-23 2001-07-03 浜松ホトニクス株式会社 光全加算器
US5136530A (en) * 1990-07-26 1992-08-04 Yao Li Ultrafast digital optical signal processing using a Venn diagram based spatial encoding technique
US5644123A (en) * 1994-12-16 1997-07-01 Rocky Mountain Research Center Photonic signal processing, amplification, and computing using special interference

Also Published As

Publication number Publication date
EP1038208B1 (en) 2003-08-27
DE69817614D1 (de) 2003-10-02
DE69817614T2 (de) 2004-06-17
CA2313241A1 (en) 1999-06-24
AU1494899A (en) 1999-07-05
WO1999031562A2 (en) 1999-06-24
EP1038208A2 (en) 2000-09-27
JP4481490B2 (ja) 2010-06-16
US6711604B1 (en) 2004-03-23
CA2313241C (en) 2005-08-23
WO1999031562A3 (en) 1999-07-29
JP2002508557A (ja) 2002-03-19

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)