GB924164A - A calculating device - Google Patents
A calculating deviceInfo
- Publication number
- GB924164A GB924164A GB4044159A GB4044159A GB924164A GB 924164 A GB924164 A GB 924164A GB 4044159 A GB4044159 A GB 4044159A GB 4044159 A GB4044159 A GB 4044159A GB 924164 A GB924164 A GB 924164A
- Authority
- GB
- United Kingdom
- Prior art keywords
- shift register
- unit
- binary
- result
- store
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
- Complex Calculations (AREA)
Abstract
924,164. Digital electric-calculating apparatus. ELEKTRONISCHE RECHENMASCHINEN-WISSENSCHAFTLICHER INDUSTRIEBETRIEB - KARL - MARX - STADT VEB. Nov. 27, 1959, No. 40441/59. Class 106 (1). In a serial calculating-apparatus performing addition and subtraction on binary-coded decimal numbers but using an adder-subtractor of pure binary type a test is made for ambiguity and correction made where necessary. Each group of four binary digits can represent a decimal digit in known pure-binary manner or a pseudo-decimal digit. Correction occurs at detection of a pseudo-decimal digit, i.e. a code representing numbers 10-15, or when carry takes place to the next denomination. A number taken from a cyclic store 2 is added to or subtract ed from a number taken from another cyclic store 1 in a unit 3 operating in pure binary serial manner. The output is fed to a shift register 7 and also to a further pure binary serial unit 8 in which it is added to or subtracted from an input of 0110, the result being fed to a further shift register 12. A control circuit 13 checks for the presence of a pseudo-decimal number or a carry in the shift register 7 and controls selector 14 to pass the corrected or the uncorrected result, as the case may be, back to the store 1. Entry to the store is adjusted for the delay in the shift registers. Modification, Fig. 5. The output of unit 3 is fed to shift register 7 and then in parallel to unit 8 and selector 14 which also receives the output of unit 8. A correction decider 73 interprets the result in shift register 7 to decide which result shall be sent on by selector 14.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEV15806A DE1099767B (en) | 1959-01-21 | 1959-01-21 | Arithmetic unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB924164A true GB924164A (en) | 1963-04-24 |
Family
ID=7575246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB4044159A Expired GB924164A (en) | 1959-01-21 | 1959-11-27 | A calculating device |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1099767B (en) |
| GB (1) | GB924164A (en) |
| NL (2) | NL244711A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2808236C1 (en) * | 2023-06-23 | 2023-11-28 | Федеральное государственное учреждение "Федеральный исследовательский центр "Информатика и управление" Российской академии наук" (ФИЦ ИУ РАН) | Self-timed single-bit quaternary adder with single spacer and increased fault tolerance |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1157008B (en) * | 1961-09-18 | 1963-11-07 | Kienzle Apparate Gmbh | Adder for dual encrypted numbers |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL91975C (en) * | 1951-09-25 |
-
0
- NL NL235929D patent/NL235929A/xx unknown
- NL NL244711D patent/NL244711A/xx unknown
-
1959
- 1959-01-21 DE DEV15806A patent/DE1099767B/en active Pending
- 1959-11-27 GB GB4044159A patent/GB924164A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2808236C1 (en) * | 2023-06-23 | 2023-11-28 | Федеральное государственное учреждение "Федеральный исследовательский центр "Информатика и управление" Российской академии наук" (ФИЦ ИУ РАН) | Self-timed single-bit quaternary adder with single spacer and increased fault tolerance |
Also Published As
| Publication number | Publication date |
|---|---|
| DE1099767B (en) | 1961-02-16 |
| NL235929A (en) | |
| NL244711A (en) |
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