GB8317749D0 - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- GB8317749D0 GB8317749D0 GB838317749A GB8317749A GB8317749D0 GB 8317749 D0 GB8317749 D0 GB 8317749D0 GB 838317749 A GB838317749 A GB 838317749A GB 8317749 A GB8317749 A GB 8317749A GB 8317749 D0 GB8317749 D0 GB 8317749D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57156662A JPS5948889A (en) | 1982-09-10 | 1982-09-10 | Mos storage device |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8317749D0 true GB8317749D0 (en) | 1983-08-03 |
GB2127246A GB2127246A (en) | 1984-04-04 |
GB2127246B GB2127246B (en) | 1985-12-11 |
Family
ID=15632554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08317749A Expired GB2127246B (en) | 1982-09-10 | 1983-06-30 | A semiconductor memory |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5948889A (en) |
KR (1) | KR840005884A (en) |
DE (1) | DE3332481A1 (en) |
FR (1) | FR2533061A1 (en) |
GB (1) | GB2127246B (en) |
IT (1) | IT1167386B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61104395A (en) * | 1984-10-22 | 1986-05-22 | Nec Ic Microcomput Syst Ltd | Dynamic type semiconductor storage device |
JPS6364695A (en) * | 1986-09-04 | 1988-03-23 | Fujitsu Ltd | Semiconductor integrated circuit |
JPH07118193B2 (en) * | 1986-09-18 | 1995-12-18 | 富士通株式会社 | Semiconductor memory device |
JPH07107797B2 (en) * | 1987-02-10 | 1995-11-15 | 三菱電機株式会社 | Dynamic random access memory |
KR910009551B1 (en) * | 1988-06-07 | 1991-11-21 | 삼성전자 주식회사 | Divided control circuit of sense amp for memory device |
JP2878713B2 (en) * | 1989-06-13 | 1999-04-05 | 株式会社東芝 | Semiconductor storage device |
KR940007639B1 (en) * | 1991-07-23 | 1994-08-22 | 삼성전자 주식회사 | Data transmitting circuit having divided input/output line |
KR0179097B1 (en) * | 1995-04-07 | 1999-04-15 | 김주용 | Data read and write method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4061999A (en) * | 1975-12-29 | 1977-12-06 | Mostek Corporation | Dynamic random access memory system |
DE2743662A1 (en) * | 1977-09-28 | 1979-04-05 | Siemens Ag | A TRANSISTOR MEMORY ELEMENT AND METHOD FOR ITS MANUFACTURING |
US4241425A (en) * | 1979-02-09 | 1980-12-23 | Bell Telephone Laboratories, Incorporated | Organization for dynamic random access memory |
JPS5616992A (en) * | 1979-07-20 | 1981-02-18 | Hitachi Ltd | Signal readout circuit |
JPS6027119B2 (en) * | 1980-04-22 | 1985-06-27 | 株式会社東芝 | semiconductor memory |
US4556961A (en) * | 1981-05-26 | 1985-12-03 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory with delay means to reduce peak currents |
-
1982
- 1982-09-10 JP JP57156662A patent/JPS5948889A/en active Pending
-
1983
- 1983-05-31 FR FR8308994A patent/FR2533061A1/en active Pending
- 1983-06-24 KR KR1019830002856A patent/KR840005884A/en not_active Application Discontinuation
- 1983-06-30 GB GB08317749A patent/GB2127246B/en not_active Expired
- 1983-09-06 IT IT22792/83A patent/IT1167386B/en active
- 1983-09-08 DE DE19833332481 patent/DE3332481A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2127246B (en) | 1985-12-11 |
IT8322792A0 (en) | 1983-09-06 |
DE3332481A1 (en) | 1984-03-15 |
IT1167386B (en) | 1987-05-13 |
FR2533061A1 (en) | 1984-03-16 |
IT8322792A1 (en) | 1985-03-06 |
JPS5948889A (en) | 1984-03-21 |
KR840005884A (en) | 1984-11-19 |
GB2127246A (en) | 1984-04-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940630 |