JPS6364695A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To speed up the action of a sense amplifier by reducing the number of power source driving transistors for the sense amplifier and arranging them around the sense amplifier. CONSTITUTION:Signals PLE and LE impressed on a gate control circuit GCONT in the sense amplifier are made H and L, respectively. FETs Q03 and Q05 are turned on, and an intermediate level determined by their ratios is supplied to the gate of a transistor Q01 connected to a driving line PSG on a higher order side by supplying the power source voltage VCC of a sense amplifier driving FETSAD. Then the signal LE becomes H to turn off the Q03, and the gate voltage of the Q01 becomes L. The conductance of the Q01 is controlled to control a driving line PSG. Thus only one the driving transistor requiring a large current amount on the higher order side suffices. A large capacity driving transistor is arranged around the sense amplifier, and a small current circuit controlling the gate is arranged separate from the driving transistor, thereby speeding up the action of the sense amplifier.

Description

[Detailed Description of the Invention] [Summary] A drive transistor circuit connected to a power supply line of a sense amplifier is placed close to the sense amplifier, and a control circuit for the gate potential of the drive transistor is placed separately. This reduces the area required or allows the use of larger drive transistors.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit that generates a clock signal that drives a sense amplifier.

[Conventional technology]

Conventionally, when reading data in a DRAM, etc., in order to detect a minute voltage difference that appears between a pair of bit lines, a sense amplifier has been made to perform a two-step operation of first preamplifying, amplifying the voltage difference to some extent, and then main amplifying. is being done.

Figure 3 shows an example of a conventional sense amplifier.
Figure (A) is its circuit diagram, and Figure 3 (CB) is its operating waveform diagram.

In FIG. 3(A), the sense amplifier (SA) is p-
chMOS FET (Ql, Q3) and n-c
Let's look at a flip-flop (F /F ) consisting of an hMOS FET (Q2.tl14 ) and its power supply drive circuit (CONT).

In the figure, F/F is connected to the high-side drive line (p-ch (jjll ground') PSG and the low-side drive line (n-ch (j,
The input point of the F/F is connected to the bit line BL and the inverted bit line BL bar (meaning a Harney inverted signal, the same applies hereinafter). The sense amplifier power supply drive circuit (CONT) is connected to a high power supply voltage Vc.
Connect its source to c, and connect its drain to the higher power supply line PS
Two p-chM OS FET connected to G:
It has Qs and Qshi. And its size is Qs<QL
At the same time, an inverted control signal PLE (brief latch enable) is applied to the gate of Qs, and an inverted control signal LE (latch enable) is applied to the gate of the other Qs.

Furthermore, an n-chM whose source is connected to the low power supply voltage Vss, whose drain is connected to the low side drive line NSC, and whose gate is applied with a control signal LE (latch enable)
OSFET: Has Qs.

In this configuration, the operation of the sense amplifier is such that during a memory read operation, the PLE signal first becomes high level, LE becomes low level, the inverted signal %PLE becomes low level, and only a small FET Qs becomes conductive. Then, the level of the high-level side drive line is slightly raised and the bit line potential difference is preamplified by the sense amplifier. Next, LE becomes high level, and the low level of its inverted signal is applied to the gate of the large FET QL, bringing the high-side drive line psc close to (rising) the high-side power supply voltage VCC. Since the potential OLE becomes high level, the impedance becomes low and lowers the level of the low-side drive line NSC.As a result, main amplification is performed by the sense amplifier.For the above operation, refer to the operation waveform diagram in Figure 3 CB). Ru.

[Problem that the invention seeks to solve]

However, the sense amplifier and the circuit that drives it (CON
It is necessary to place it adjacent to T).

This is because a large current flows through the sense amplifier drive lines PSG and NSC, so that the wiring lengths thereof are required to be as short as possible. Therefore, it is necessary that the sense amplifier drive circuit has the same pitch as the width of the sense amplifier. However, since the sense amplifier drive circuit has three FETs and occupies a fairly large area, it is difficult to use large FETs as the drive FETs Qs and QL, and the operation of the sense amplifier cannot be sufficiently controlled. This was an obstacle to achieving high speed.

[Means for solving problems]

The present invention provides a semiconductor integrated circuit characterized in that a power supply drive transistor circuit of a sense amplifier is arranged close to the sense amplifier, and a control circuit for the gate potential of the drive transistor is arranged separately from this. It is something.

[Effect]

According to the above configuration, the number of drive transistors that need to be placed close to the sense amplifier can be reduced by one compared to the conventional one, and the circuit area can be reduced, or by using a larger drive transistor, the sense amplifier can be The high speed ratio of the operation can be achieved.

〔Example〕

An embodiment of the present invention is shown in FIG. 1, with FIG. 1(A) showing a circuit diagram of the embodiment, and FIG. 1(B) showing an operation waveform diagram of the embodiment.

In FIG. 1A, the number of transistors on the high-level drive line is reduced to one instead of the conventional two, and the gate of the FET QOI is controlled so that the transistors serve as the two transistors. Here, in E1 diagram (A), Qol is p-ch
It is a MOS FET, and its source is connected to a high-level power supply voltage Vcc, and its drain is connected to a high-level side drive line PSG. And its gate is p-chMo SFET of gate control circuit: FET in parallel with QO3
: Connected to QO4 and QO5 at the connection point O. In this gate control circuit, the gate of FET:QO3 is connected to control signal LE, the gate of FET:QO4 is connected to control signal LE, and the gate of FET:QO5 is connected to control signal PLE. The lower drive line NSC is the same as the conventional example shown earlier, and FET':QO2 is as shown in FIG.
This corresponds to Qs in A), and LE is applied to its gate.

FIG. 1(B) shows an operating waveform diagram of the above circuit, and will be explained below.

■ PLE becomes high level at tl, FET:QO5
conducts. At this time, since LE is at low level, p-
chF ET: QO3 is conducting.

As a result, an intermediate level determined by the ratio of QO3 and QO5 appears at connection points.

■ At time t2, LE becomes high level and p-chFE
T:QO3 is blocked, n-chFET: Q0
4 is conductive. Therefore, the connection point O becomes low level.

As a result, a step-like waveform is output at the connection point.

And that is the p-c connected to the higher side drive line PSG.
hF ET : Applied to the gate of Q 01 at time 1. , the QOI conductance is relatively small, and the time t
2 gives greater control. Thereby, desired sense amplifier drive line control is performed.

Here, in the 11th ffl (A) circuit, the QOI of the FET that directly drives the drive lines PSG and NSC of the sense amplifier,
QO2 is required to have a large size as in the past, and must be placed adjacent to the sense amplifier in order to shorten the drive lines PSG and NSC. However, the gate control circuit (FET
Since the current of the signal line connecting QO3, QO4, Q05) and QOI, QO2 is sufficiently small, there is no particular restriction on its length. Therefore, as shown in FIG. 2, which shows the overall layout of the memory, the gate control circuit GCON of the sense amplifier drive circuit
T can be separated from the drive FET section (SAD) and placed in any other area of the memory. Here, the drive FE
The T section (SAD) requires only two FETs, one less than the conventional one, so when using FETs of the same size as the conventional one, the circuit area can be small, which is advantageous for increasing the memory capacity. Alternatively, if the circuit area is the same as the conventional one, it is possible to use a correspondingly larger transistor, increase the drive capability of the sense amplifier, and increase the speed of the memory. Another advantage is that the number of control signals for the sense amplifier drive circuit is two, one less than the conventional example shown in FIG. 3(A). In FIG. 2, 1.1" is a cell area, SA is a sense amplifier row, and WDEC is a word decoder. The drive FET section (SAD) is surrounded by the width of the word decoder WDEC and the width of the sense amplifier. It is contained within the area.

The above explanation is based on the p-
This was the case when a stepped waveform was added to the gate of chFET.

FIGS. 4(A) and 4(B) show a circuit diagram and an operation waveform diagram of another embodiment of the present invention. Figure 4 (A), (B
), p-chFET QO3, QO4
are connected in parallel to the connection point with n-ch FET QO5), and the LE bar and Q04 are connected to the gates of QO3 and QO5.
By adding a PLE bar to the gate of
A similar effect can be achieved by adding a stepped waveform to the gate of the n-ch FET connected to the SC.

〔Effect of the invention〕

As described above, according to the present invention, the number of large transistors that drive the sense amplifier can be reduced compared to the conventional one, and the circuit area can be reduced accordingly to achieve a high circuit integration, or the transistor size can be increased to It is possible to increase the speed of amplifier operation. Another advantage is that the control signal for the sense amplifier drive circuit only needs to be two-phase.

[Brief explanation of drawings]

FIG. 1(A) is a circuit diagram of an embodiment of the present invention, FIG. 1(B)
is an operating waveform diagram of the embodiment of the present invention, FIG. 2 is an overall layout diagram of the memory of the embodiment of the present invention, FIG. 3(A) is a circuit diagram of a conventional sense amplifier, and FIG. 3 (CB) is a conventional circuit diagram. FIG. 4(A) is a circuit diagram of another embodiment of the present invention, and FIG. 4(B) is an operating waveform diagram of another embodiment of the present invention. 5A--Sense amplifier PSG--One high-side drive line N5C-One Low-side drive line S A D-One-Sense amplifier drive FETG CON
T---Gate control circuit PLE-Control signal (Brief latch enable signal) L E-Control signal (Latch enable signal) Patent applicant Fujitsu Co., Ltd. (N':h) Agent Patent attorney
Gobe Tamamushi (1 other person) SAD-1-GCONT Shihi (8) tlt2 Circuit diagram and first 11 waveform diagram of the embodiment of the present invention No. 1
Figure C0NT Overall layout explanatory diagram Figure 2 Figure 2 Circuit 121 of conventional example and spinning waveform opening 3 Figure

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that a drive transistor for a power supply line of a sense amplifier is arranged close to the sense amplifier, and a control circuit for a gate potential of the drive transistor is arranged separately from the drive transistor.