KR930005779Y1 - Semiconductor memory element - Google Patents

Abstract

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Description

Semiconductor memory device

1 is a circuit diagram of a conventional semiconductor memory device.

2 is a circuit diagram of a semiconductor memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

A: Bit line control unit B: Bit bar line control unit

1N ₁ to 1N ₃ , 2N ₁ to 2N ₃ , 3 to 9, 14, 16: EnMOS transistor

1P, 2P, 10-12, 13, 15: PMOS transistor

The present invention relates to a semiconductor memory device, and in particular, a flash clear (1) by adding one external signal to reduce the required time by using “0” (zero) data or “1” (one) data in all of the memory devices. The present invention relates to a semiconductor memory device having a Flash Clear) function.

In the conventional semiconductor memory device, as shown in FIG. 1, the bit line BIT is connected to the drain of the NMOS transistor 1 and the NMOS transistor 4 of the source of the NMOS transistor 5, and the PMOS transistor ( 11 is connected to the drain terminal of the bit line, ) Is connected to the drain terminal of the NMOS transistor 2 and the source terminal of the NMOS transistor 8 and the NMOS transistor 4, and to the drain terminal of the PMOS transistor 12, and the flash clear bar signal FC ) Is connected to the gate of the PMOS transistor 10, the source terminal of the PMOS transistor 10 is connected to the power supply (Vdd), the flash clear signal (FC) is the gate and PMOS transistor of the NMOS transistor (2) The gates of (11, 12) and the gates of the enmos transistors (1, 2, 3) are simultaneously connected, and the BLEQ signal is applied to the gates of the enmos transistors 4, Connected to the power supply Vdd through the NMOS transistor 9, and a source terminal of the NMOS transistor 3 is connected to the gates of the NMOS transistors 4 and 8 to be connected to the word line W / L. Connected and enmoose tran The drain of the master 5 is connected to the drain of the enmos transistor 6 and the power supply Vdd, and is connected to the gate of the anMOS transistor 7, and the drain of the enMOS transistor 8 is connected to the drain of the enMOS transistor 7. The drain and power supply Vdd are connected to the gate of the NMOS transistor 6.

That is, in the related art, the bit line is connected to the NMOS transistor 1 and the bit bar line is connected to the NMOS transistor 2 to be controlled by the flash clear (FC) signal.

The operation state of the configuration circuit will be described below. When the Flash Clear is in the Flash Clear state, the flash clear signal (FC) is "high" and the flash clear bar signal ( ) Becomes "low". Therefore, the word line W / L is " high " by the enmos transistor 3 and " on " and the enmos transistors 1 and 2 are " on " by the flash clear signal FC. Line (BIT) is "low", bit bar line ( ) Becomes " high " so that the memory cell is fixed at zero.

At this time, the PIOS transistors 11 and 12 are in an "off" state. However, in the conventional circuit as described above, when the flash clear mode is set, the bit line (BIT) is fixed to "0" (low) and the bit bar line (BIT) is fixed to "1" (high). There were possible disadvantages to this.

The present invention is devised to solve these disadvantages and will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 2, the data input signal D is applied to the gate of the PMOS transistor 13 and the NMOS transistor 14 and the connection point of the PMOS transistor 13 and the NMOS transistor 14 is shown. The output is connected to the gates of the PMOS transistor 1P and the NMOS transistor 1N ₃ of the bit line Jay portion A, the source of the PMOS transistor 1P is connected to the power supply Vdd, and the drain thereof is flash cleared. The signal FC is connected to the drain of the NMOS transistor 1N ₃ through the NMOS transistors 1N ₁ and 1N ₂ , which are applied as gates, and the data input bias ( ) Is applied to the gate of the PMOS transistor 15 and the NMOS transistor 16 and the output of the connection point of the NMOS transistor 16 of the PMOS transistor 15 is the NMOS transistor (B) of the bit bar line controller B. 2P) and the gate of the NMOS transistor 2N ₃ , the source of the PMOS transistor 2P is connected to the power supply Vdd, and the drain thereof is the NMOS transistor 2N ₁ , to which the flash clear signal is applied to the gate. 2N ₂ ) and is connected to the drain of the NMOS transistor 2N ₃ , and the connection point outputs of the NMOS transistors 1N ₁ and 1N _{2 are} between the NMOS transistor 5 and the source terminal of the NMOS transistor 4 and PIM. is connected to the drain of the agarose transistor 11 connected to the bit line (bIT) and, yen Mohs transistor source end and the connection point of the output (2N _1, 2N ₂₎ is yen Mohs transistor 8 yen Mohs transistor 4 The drain is connected to the coat of agarose transistor 12 bits at ( ), A BLEQ signal is applied to the gate of the NMOS transistor 4, a flash clear signal FC is applied to the gates of the PMOS transistors 11 and 12, and a source end thereof is connected to the gate of the NMOS transistor 9. The flash clear signal FC is connected to the power source Vdd, and the flash clear signal FC is applied to the gate of the NMOS transistor 3, and the source of the NMOS transistor 3 is connected to the gates of the NMOS transistors 5 and 8 so as to form a word line. (W / L) and the drain of the NMOS transistor 3 are the flash clear bar signal ( ) Is connected to the drain of the PMOS transistor 10, which is applied to the gate, the source of the PMOS transistor 10 is connected to the power source Vdd, and the ins of the NMOS transistors 5 and 7 are the power source Vdd and N The drain transistors 6 and 7 are connected to the drains of the MOS transistors 7 and 6, respectively. In other words, the present invention is a flash clear signal (FC) and data (D, Is controlled by bit lines (BIT) and bit lines ( ) To "high" or "low".

The operation state of the configuration circuit will be described below.

When the flash clear signal FC becomes " low " and enters the normal mode, the bit line controller A and the bit bar line bare part B are connected to the bit line BIT and the bit bar line (B). ) Does not have any effect.

On the contrary, when the flash clear signal FC becomes "high", it is in the flash clear mode. That is, when the flash clear signal FC becomes "high", the PMOS transistors 11 and 12 are "off" so that the bit line load is the bit line (BIT) and the bit bar line ( ) Is not connected.

In addition, the NMOS transistors 1N ₁ , 1N ₂ , 2N ₁ , 2N ₂ are “on” by the flash clear signal FC that is “high” so that the bit line BIT and the bit bar line ( ) State of data input signal (D) and data input bar (Bar) signal ( Depends on).

In other words, to write 0 (zero) to all memory cells, give "0" (zero) to the data input (D). To write "1" (one), write "1" to the data input (D). You can give it. It is possible to initialize all memory cells as "0" or "1" as data of a normal input terminal.

Enmos and PMOS transistors of the bit and bit bar line controllers added in the present invention do not affect the overall chip size because only one portion is required in one column.

In other words, the present invention requires an external signal to add a flash clear mode, and according to input data, all memory cells can be cleared as desired.

Claims (1)

In a semiconductor memory device whose bit line and bit line states are controlled by the flash clear signal FC, the bit line control unit A and the data input bar signal (operated and controlled by the data input signal D) Flash clear selection circuit (FC) and data input (D, Bit line (BIT) and bit bar line () A semiconductor memory device, characterized in that it is configured to control the state.