DE3332481A1 - SEMICONDUCTOR STORAGE - Google Patents

Description

The invention relates to a semiconductor memory as specified in the preamble of claim 1 is.

A dynamic random access memory as shown in FIG. 1, which consists of a number of insulated gate field effect transistors (hereinafter referred to as "MOSFETs") has been proposed earlier.
In a dynamic random access memory (RAM) of the type described, the memory cell array M-ARY consists of a number of memory cells, each of which has a data storage capacitor Cs and an address selection MOSFET Q, these

Cells are arranged in a matrix, as well as from a Number of complementary data line pairs D, D and a number of word lines W.

A memory cell array M-ARY also has dummy cells DMC ("dummy cells"), which are located at the crossover points between dummy word lines and complementary Data line pairs are arranged around a reference voltage for the detection of a read signal from the Generate memory cells. Each of the dummy cells DMC is made under the same manufacturing conditions and the same Construction constants like the memory cells made with the exception that the capacitance of the capacitor is about half that of the capacitor Cs of the memory cell.

If accordingly to one of the data lines D

(D) connected memory cells are selected, those connected to other data lines D (D) become

Blind cells selected simultaneously. The read signal level from the memory cells and the reference voltage ng from the dummy cells are transmitted to sense amplifiers SA and are amplified by the amplifiers. Each sense amplifier SA consists of a pair of MOSFETs Q ₁ and Q_ which are cross-connected with each other and the positive feedback operation of these transistors differentially amplifies any weak signal. This positive feedback mode is initiated simultaneously when a MOSFET Q _q , which is arranged together with the sense amplifiers of the other data line, is made conductive by a sense amplifier control signal φ. Based on the potential difference between the read signal level from the memory cells and the reference voltage from the dummy cells given at the time of addressing, the potential of the data line having the higher potential falls at a slower speed and the potential of the lower potential '.

having data line falls at a higher speed due to the positive feedback mode of operation, while the potential difference increases. The positive feedback mode is approaching End when the potential of the data line, which has a lower potential, is lower than the threshold voltage of the MOSFETs, so that the potential of the data line having the higher potential at a predetermined high level remains, whereas the potential of the data line having the low potential eventually reached 0V. The read signals of the complementary data line pairs D, D only the signals selected by a column switch C-SW are sent to the common data line pairs CD, CD transmitted and generated by a main amplifier and a data output buffer DOB.

The reference symbol RC-DCR denotes a decoder circuit which generates the selection signals for the word lines and forms a data line in accordance with the address signals of an address buffer ADB.

As a result of studies, the inventors of the present invention have found that then, when sense amplifiers of the type described above are used, the following problems arise.

When an address strobe signal RAS goes low as shown in the timing chart of Fig. 2, each circuit for the word line selection process starts to operate. This working current causes a voltage drop in a power supply line, so that the ground potential V and a power circuit V _cc change.

Thereupon, the potential V of the selected word line rises when the potential of the word line selection clock signal φ rises. The word line has a line resistance and a parasitic capacitance. For this reason, when the potential of the word line rises, this rise is rapid in the "vicinity of the decoder circuit CR-DCR, as shown by the solid line, but slow in those parts separated from the decoder circuit, as shown by the dash-dotted line. Accordingly, the potential of the reader amplifier control signal φ increases ,

pa

after the memory cells connected to the removed part of the word line are selected.

When the potential of the sense amplifier control signal φ is raised in this way, start

P ^a _

the sense amplifiers connected to the complementary data line pairs D, D together

mentioned process of positive feedback, so that the potential V _, _, of the semiconductor substrate through capacitive coupling with the data lines is reduced.

As a result, the reference _{voltage V re} £, caused by voltage division of the aforementioned voltages V and V changes

OO S S

will move toward the low level side due to the capacitive coupling with the semiconductor substrate. This reference _{voltage V f} is used to determine the input signal level of the address buffer ADB and the data input buffer DIB. Accordingly, the address buffer ADB and the data input buffer DIB perform such an operation as to misjudge the high level even though the external address signals YA and the written data signal D. are low.

The point in time of the change in potential of the sense amplifier control signal φ essentially falls

pa

together with the time at which the CAS system (data line) Address signals, i.e. the column address signals YA are taken into the address buffer ADB, when the address strobe signal CAS is low.

For this reason, there is a high possibility that the above-described failure will occur.

Furthermore, it is necessary to set the word line selection clock signal φ synchronously with the selection time of the memory cells which are connected to the parts remote with respect to the decoder circuit CR-DCR. Therefore, the timing control is difficult to perform. There is a relatively large production variance for the line resistance

■ J.-19 _

and the parasitic capacitance of the word line, so that there is also a deviation for the selection timing of the memory cells located on the remote parts of the word line. Accordingly, a sufficient margin is generally ensured for a time delay T between the occurrence of the word line selection clock signal φ and the occurrence of the sense amplifier control signal φ with regard to the deviation described above. Because of this time delay, reading the memories becomes slow.

Another problem is that the number of circuit elements such as inverters for the formation of the delay circuit increases and the consumed current becomes much larger because the delay time T, must be set sufficiently large.

The present invention is directed to those described above by the inventors of this invention • Eliminate identified problems. It is an object of the present invention to provide a Indicate semiconductor memory in which the occurrence of malfunctions due to the operation of the sense amplifiers is drastically reduced.

It is further an object of the present invention to provide a semiconductor memory capable of high speed operation realized.

It is another object of the present invention to specify a semiconductor memory in which the number of circuit elements such as the consumed current is reduced are.

These and other objects of the invention will become apparent from the following description in conjunction with FIGS

- - 20 -

accompanying figures

Fig. 1 shows a circuit diagram of a dynamic memory ¹ with w.ahlfreiem access, as was proposed in the past

Fig. 2 shows a timing diagram for explaining the dynamic memory with random access according to FIG. 1 FIG. 3A shows a circuit diagram of a dynamic Random access memory

Provision of an embodiment of the present invention

Fig. 3B shows a timing chart for explaining the address setting process of the dynamic memory with optional

Access to Figure 3A

4 shows a circuit diagram of a memory cell array M-ARY and a sense amplifier SA shown in Fig. 3A

FIG. 5 shows a timing diagram for explaining the operation of the memory cell array M-ARY and the sense amplifier SA according to FIGS. 4 and
6 shows a perspective cross-section,

which shows an example of the structure of the memory cell element.

Fig. 3A is a circuit diagram of a dynamic random access memory (a dynamic memory . with random access in an arrangement with data lines laid in parallel, “folded bit line”) according to one Embodiment of the present invention.

The semiconductor memory of this embodiment uses the so-called two-zone system (two-mat system), but it is not limited to this. The semiconductor memory has a total of 64 Kbit memory cells. Each of the memory cell arrays (memory cell arrays M-ARY1, M-ARY2) has memory cells arranged in 128 rows and 256 columns and a storage capacity of 32 768 bits (32 Kbit). The main circuit blocks in the drawing are consistent with the geometric arrangement in one actually implemented semiconductor integrated circuit (hereinafter referred to as IC).

128 decoded output signals, which are obtained by decoding external digit address signals A _Q to Ag, are applied to the row address selection lines of each memory cell array M-ARY1, M-ARY2 by row decoders (which also serve as word line drivers) R-DCR1, R-DCR2.

A column decoder C-DCR decodes external column (data line) address signals A _g to A ₁₅ and produces 128 decoded output signals. Each of these decoded column select output signals is common to four columns, ie columns of the right and left memory fields and adjacent upper and lower columns within each memory field.

The internal address signals A_ and A "are used to select any one of these four columns. In other words, these external address _{signals A 7} , Ag are applied to a signal generator φ ..- SG. The signal generator & „4a ~ SG decodes the external address _{signals A 77} Ag and forms four column selection signals ^ yOO '^ yOV ^ yIO ^and ^ yH * ^s P ^{old selection switches} CSW-S1, CSW-S2 select one column from the four through the external

Address _{signals A g} to A ₁₅ from in accordance with the column _{selection signals} 0 yOQ ^ 0 _yQ1 , 0 _y1Q , φ _γ ^.

As previously described, the decoder is for selecting the columns of the memory cell arrays in two Levels, i.e. the column decoder C-DCR and the column selection switches CSW-S1 and CSW-S2. The decoder is divided into two stages for the following reasons. First of all, it must be within a IC chip wasted space can be eliminated. In other words, the pitch a NOR gate, which has a relatively large area for a pair of right and left output signal lines of the column decoder C-DCR in the longitudinal direction in accordance with the column arrangement pitch of the memory cells are brought.

If the decoder is divided into two stages, the number of MOSFETs forming a NOR gate can be can be reduced and the area occupied by them can also be reduced.

The second reason is that the load on an address signal line weakens and the switching speed of the address signal is increased by the number of on an address signal line to be switched NOR gate is reduced.

The address buffer ADB generates eight outer address signals A _Q to A ₇ and Ag to A ₁ ^ / which in eight kinds of respectively complementary address signals (a _Q , ä _Q ) to (a ₇ , U ₇ ) and (ag, ag) to Ca ₁₅ , iL ₅ ) and applies them to the decoder circuit in synchronism with the clock signals φ ,

ar

φ and in accordance with the switching process ac

inside the IC chip.

The character CSG denotes a control signal generator, which the address selection (strobe-) Signals RAS, CAS and the write enable signal WE receives and various ones described above and generates signals to be described below.

Figure 3B is a timing diagram of the dynamic random access memory of Figure 3A.

The circuit operation of the address setting process in the dynamic RAM described above, referring to the timing chart of Fig. 3B.

First, the control signal generator CSG lifts

the address buffer control signal φ to the high

ra level in accordance with the change of the address strobe signal RAS of the line system to the low level. In this case, seven kinds of complementary paired address signals (a ″, a_) to (a _ß , a _g ) are applied from the address buffer ADB to the row decoders R-DCR ₁ , R-DCR ₂ via the row address line R-ADL.

The word line selection clock signal φ is then raised to the high level, so that the row decoders R-DCR ₁ , R-DCR _{2 become} active and each word line is selected from a plurality of word lines of each memory cell array M-ARY-, M-ARY ₂ and is raised to the high level.

In accordance with the change in the address selection signal CAS to the low level, the control signal generator raises CSG the address buffer control signal

φ of the column system to the high level so that ac

seven kinds of complementary paired address signals (a _g / a _g ) to (^ ₁₅ , ^a -ic) r which the external

Corresponding to column address signals A _g to A ₁₅ , from the address buffer ADB via the column address line C-ADL to the column decoder C-DCR.
As a result, the potential of one output signal line of a pair of 128 pairs of output signal lines of the column decoder C-DCR becomes high level. The high level signal is applied to the column selection switches · CSW-S. and CSW-S _{2 are applied} through this pair of output signal lines.

The column switch selection clock signal φ is then raised to a high level so that the signal generating circuit φ. .-SG is put into operation.

On the other hand, the complementary pair of address _{signals (a 7} , a _? ) Corresponding to the external address signal A_ has been applied to the signal generator circuit 52S ..- SG when the address buffer control signal φ has the high level

ar

and the complementary pair of address signals (ag, ag) corresponding to the external address signals Ag are applied when the address buffer control signal φ becomes high level.

ac

When the column switch selection clock signal φ is raised to the high level, the signal generator circuit φ ..- SG therefore essentially simultaneously supplies the column selection signals to the column selection switches CSW-S ₁ , CSW-S ₃ .

In other words, the signal generator circuit φ ..- SG raises the potential of a column selection ignales to the high level in accordance with the external address _{signals A 7} , Ag synchronously with the column switch selection iTaktsignal φ.

4.25 ---

* 9

In the column selection switches CSW-S ₁ , CSW-S-, four MOSFETs are turned on, the gates of which are connected to a pair of output lines in which the potential is raised to a high level among the 128 pairs of output signal lines of the column decoder C-DCR. The high level column selection signal is applied to the column switch C-SW- or C-SW ₂ through one of these four MOSFETs.

In this way, a pair of MOSFETs is selected from a total of 512 MOSFET pairs in the column switches C-SW ₁ , C-SW ₂ and switched on, so that a pair of complementary data lines D, D in the memory cell array with the common data line pair CD , CD to be connected.

FIG. 4 shows an example of a memory cell array M-ARY and sense amplifiers SA.

In the manner already described, the memory cell array M-ARY consists of a large number of in a matrix arranged memory cells MC, each of which consists of a data storage capacitor C and an address selection MOSFET Q, and complementary data line pairs D, D and from word lines W.

At the crossover points between dummy word lines and the complementary ones described above Dummy cells DMC are arranged in pairs of data lines, which provide the reference voltage for

3Q len the read signals from the memory cells are used.

Each dummy cell is made under the same production conditions and with the same construction constants manufactured like the memory cells MC with the exception

that the capacitance of the capacitor is essentially half the capacitance of the capacitor C _{3 of} the memory cell.

If the memory cells connected to one of the data lines D, (D) are selected, so the dummy cells connected to the other data lines D, (D) are selected simultaneously. Accordingly, the read signal level from the memory cells and the reference voltage of The dummy cells are transmitted to the sense amplifiers SA and amplified by these amplifiers.

Each sense amplifier SA consists of a pair of cross-wired MOSFETs Q ₁ and Q ₂ , and a weak signal is differentially amplified by means of the positive feedback mode of operation.

In these embodiments, the source electrodes of the MOSFETs Q-, Q ₂ , which form each sense amplifier, are connected in common, and there is a MOSFET Q ₁ - at the common source electrode for receiving the sense amplifier control signal φ

arranged. A similar MOSFET Q ₁₁ is arranged in a similar manner with the MOSFETs Q ₃ , Q., which form the other sense amplifier. Likewise, a MOSFET is provided for receiving the sense amplifier control signal φ for each sense amplifier, pa

The wiring for applying the sense amplifier control signal φ to the gates of the MOSFETs Q _1n Q ₁₁

pa "^ f ι ·

ua has the same structure as that of the word lines. If the word line consists of an electrically conductive poly-silicon layer which is formed integrally with the gate electrode of the address selection MOSFET of the memory cell, for example, the gate electrodes of the MOSFETs Q ₁₀ Q ₁₁ and the like and the common wiring for them are integral the electrically conductive polysilicon layer is formed.

Λ § B 5-11

_s .a, ■; _; - - _ö; Jübglfens is started Ietrlebswelee _s of the positive HüokkQpplung simultaneously when; these MOSPETs (pi) _% r _t ^ ₁ Qf] Qf Q ^ i ^u «Μ * by the reading amplifier interference signal o *:" SfM ^ gft Ifi | end. fsmaehfe. At. time _; ..the addressing,

Blind ^ ellen; are selected ,, ΐΡ ^ βηδΙβΙ.νΑ.ήΓ -. ^ ΒβνΗιΒΗβϊβ.,. Ρρί, ^ ο ^ ΙβΙ have »

with a nledrlg.f ren _f .ßesehwinäas fotefltial dor other data line, 1 © d ^ 4M , ai © drif © re? © teßtlal · , hat ^. fjllt ^ fit one, σ ,, - _1ΑΓ , i- ^ Jhfjjfreiflr, Qgfieh ^ indlgkfit-, from ,, due to the potential- .. ", ₀ p, d | ff er © nz. between de ^ f aar of data lines, i7s-v, nr; -r ^ i ^ ^e M IiS ^ ^ between them di <9- fotent4.aj.dlfferenz

go to

Data line that has a potential .. * punter. © _di:; Schwe 11 tension öi «: -; ::% BP.; Jr» ^w «i ^e ft ': - ^ft fe || i ^ Hfc # -. FPb that the potential / r of the data

Jherc has potential on one ^ yerbleibti -. ^ hrgnd the Pot ^ ftial

.V erjcelp ^ * .-; .,.: .- ·.

den: so reinforced _; Loose signals of the complete data line, ρ # D _:. only those that are selected by the column switch C-SW,

ν (? p, CO transferred "ο., ρ sÄ ^ Äa ^ ift ^^ _; ^ fß ^ main yoyf stronger MA. and-d © n _r. data output ·

nale ras. _KC ; CIs and _i: .u control signals

Perspective cross-section of the flower structure - the one previously described

In the drawing, reference numeral 1 denotes a P-type semiconductor substrate; with 2 is a relatively thick insulation film (hereinafter FeId insulation film called) denotes; 4 and 5 are

. 5 N -like semiconductor regions, with 6 being a conductive one Denotes polysilicon layer of a first conductivity type; 7 is an N-type surface inversion layer; 8 is a conductive polysilicon layer of the second conductivity type; 9 is a phosphosilicate glass (PSG) layer, and 10 denotes an aluminum layer. The substrate, source area, drain area, gate insulation film and gate electrode of the address selection MOSFET Q

are formed with the above-mentioned P-type semiconductor substrate 1, the N-type semiconductor region 4, the N -type semiconductor region 5, the gate insulating film 3 and with the polysilicon layer 8 of the second line type. The conductive polysilicon layer 8 of the second conductivity type is used as a word line. The aluminum layer connected to the N -like semiconductor region 5 10 is used as a complementary data line D or D.

In the case of the data storage capacitor C in the memory cell, the electrode is through the conductive polysilicon layer 6 of the first conductivity type, which the electrical layer through the gate insulation f ilm 3 and the other electrode through the N-type surface inversion layer 7 previously has been described. In other words:

Since the source power voltage V is applied to the conductive polysilicon layer 6 of the first conductivity type "induces" this voltage V. across the gate

OO

Insulation film 3 on the surface of the P-type

Semiconductor substrate 1 has the N-type inversion layer 7.

The gate insulating films, gate electrodes and the common wiring for the MOSFETs QiQ Q ₁₁ and others arranged in the respective amplifiers are made in the same manner as the insulating film 3 and the conductive polysilicon layer 8 of the second conductivity type described above , educated. Therefore, when a molybdenum-silicon (Mo-Si) layer is formed on the surface of the insulating film 3 to lower the resistance of the word line, the same Mo-Si layer is formed on the gate electrodes of the MOSFETs Q ₁₀ / Q ₁₁ and formed on their common conductor tracks.

In Fig. 4 is the sense amplifier control signal

φ applied from the same direction as the word pa

line select signal. In other words, the sense amplifier control signal φ becomes from the same side

pa

like the row decoder R-DCR (also serving as word line driver).

A precharge circuit PC is provided for each complementary data line pair. This circuit receives a precharge pulse φ and applies the

pe source supply voltage V to the complementary Data line pair in the same way as to the

MOSFETs QJ ₇ / Q ₁₈ f which is shown in FIG. This precharge pulse φ 'reaches the high level,

pe

when the address select signal is raised to the high level, and it turns on the MOSFETs Q ₁₇ / Q ₁₈ et al, so that it makes them precharge the complementary data lines D ₁ , D et al. Reset MOSFETS Q _ to Q are on the relevant

Ij 16

lent the decoder circuit R-DCR a remote side arranged each word line. If the address selection

signal is raised to the high level, these MOSFETs are turned on and quickly set the Word lines from the selection state to the non-selection state.

In this embodiment, a similar reset MOSFET Q ″ is arranged on a signal line of the sense amplifier control signal φ because the

pa

MOSFETs Q must be ₁₀ Q ₁₁ off among other things quickly, lest the precharge circuits PC prevents the ON state of the MOSFETs ° -in 'Qii ^ ^s pre-charging.

The clock signal φ controls the operation of the reset MOSFETs.

The operation of selecting the memory cell and the operation of the sense amplifiers in the one described above Example is described below under the timing diagram of FIG.

The potential V. the word line selected by the rise in the potential of the word line selection clock signal φ rises. The word line has a line resistance and a parasitic capacitance. For this reason, the potential applied to that part of the word line that is remote from the decoder circuit R-DCR rises with a delay in accordance with the dashed line, while the potential of the selected word line in the vicinity of the output terminal of the decoder circuit R-DCR in accordance with the The solid line in the timing diagram increases rapidly. In other words, the potential of the word line changes in the vicinity of the output terminal of the decoder circuit, which is connected to the word line for the transmission of the selection signals formed in it to the word line, in the manner shown in the timing diagram by the

solid line manner, while the potential of the removed from the output terminal lying word line changes in the manner indicated by the dashed line.

In this embodiment, the sense amplifier control signal φ becomes in accordance with

pa

the selection process of the memory cells carried out, which on the word line in the vicinity of the Decoder circuit R-DCR are arranged. In this case the sense amplifiers start in the neighborhood of the decoder circuit R-DCR performs the positive feedback operation because the sense amplifier control signal

φ increases rapidly, as indicated by the solid pa

Line is shown in the drawing. In contrast, the sense amplifiers which are arranged at the parts remote from the decoder circuit R-DCR start the process of positive feedback delayed because the sense amplifier control signal φ rises with a delay, as indicated by the gepa

dashed line is shown in the drawing.

In this way, the sense amplifiers start the process of positive feedback in accordance with the propagation delay time of the clock signal φ

P ^a on the sense amplifier control signal line (delay line), that is, in synchronism with the selection timing of the respective word lines over a relatively long period of time T. In other words, the memory cells and the dummy cells are sequentially selected from those located in the vicinity of the decoder circuit R- DCR are arranged up to the removed parts, and according to the selection, the sense amplifiers sequentially begin the process of positive feedback from the sense amplifier SA256, which is located in the vicinity of the decoder switch.

device R-DCR is arranged, bsi to the sense amplifier SA1, which is arranged in a remote area.

This arrangement makes it possible to reduce the potential drop of the potential V _._ of the semiconductor substrate, which occurs due to the capacitive coupling between the semiconductor substrate and the data line, to reduce. As a result, the level change of the reference voltage V- can also be reduced so that an erroneous operation at a time when the column address signals and the written data signal is taken into the address buffer ADB and the data input buffer DIB, can be prevented.

The time at which the sense amplifier control signal Φ _ must be generated must correspond to the time for selection P ^a

of the memory cell in the vicinity of the word line, so that timing control becomes easy. When the word line and the signal line for the transmission of the sense amplifier control signal φ

formed simultaneously with the previously known manufacturing techniques for integrated semiconductor circuits becomes, the resistance and the parasitic capacitance of the word line change easily due to it of deviations in production conditions and ver- causes a similar change in the resistance and the parasitic capacitance of the signal line. If the characteristic quantities of the delay of the Word line itself due to 'deviations in production conditions change, the characteristic quantities for the delay of the signal line change corresponding. When the memory cell selection time changes due to variances in production conditions changes, the operating time of the sense amplifiers changes accordingly.

In this way, a discrepancy in the point in time when the word line is selected is compensated for by a discrepancy in the time at which the sense amplifiers are used. Furthermore, the delay time T, of the sense amplifier control signal φ., With respect to the

pa

Word line selection clock control signal φ can be shortened, so that the structure of the delay circuit for forming the sense amplifier control signal φ simplified and its power consumption pa

can be reduced.

The present invention is not restricted to the exemplary embodiments described above. The MOSFETs Q ₁ -. Q ₁₁ can be through MOSFETs with

IU / Il

relatively small line characteristics and MOSFETs with relatively large line characteristics are replaced in a parallel arrangement, so that the sense amplifier control signal φ to the MOSFETs with re-

pa

relatively small line characteristics is applied, while the delayed signal of the sense amplifier control signal φ to the MOSFETs with relatively large

pa

Conductivity values can be applied. This arrangement can suppress the drop in the high level potential of the data line reduce the sense amplifier at the start of the positive feedback process. Since the data stored in the memory cells corresponding to the high level is repeatedly read and are written, they can be easily read out as data corresponding to the low one. To such a one To prevent faulty operation, an active back storage circuit can be installed on the complementary data line pair be arranged. Such an active restore circuit is detailed in Japanese patent application 209397/1981 by Hiromi MATSUURA, dated December 25, 1981, entitled "Dynamic Integrated

RAM circuit device ". For this reason, the explanation of the circuit is made here omitted.

The structure of the memory field can be changed in several ways.

In addition to a dynamic RAIL, the present invention can also be applied to semiconductor memories such as a RAM with sense amplifiers on the data lines, a ROM (read only memory), etc. can be used.

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Claims (22)

* J W yJ ί. STREHL SCHUBEL-HOPF SCHULZ WIDENMAYERSTRASSE 17. D-8000 MUNICH 22 HITACHI, LTD. / DEA-26118 September 8, 1983 SEMI-CONDUCTOR MEMORY \.) Semiconductor memory characterized by: a memory field with a number of memory cells (MC) each having a select terminal and an output terminal and in are arranged in a matrix a number of word lines (W) which are provided for each row of the memory cells (MC) and to which the selection terminals of the number of memory cells are connected and with a number of data lines (D), one of which each is provided for a column of the memory cells and to which the output terminals of the plurality of memory cells are connected with a selection circuit (R-DCR) having a number of output terminals each of which is connected to one end of a word line and which has a selection signal for selecting forms a memory cell row from a plurality of memory cell rows with a number of sense amplifiers SA, each of which is provided for a memory cell column and to whose input / output connections the data lines for the memory cell columns and control connections are connected with a control device CSG for applying control signals (φ ) to the control connections of the reading pad amplifier (SA) so that the working of the sense amplifier is started at times that vary from one another. 2. Semiconductor memory according to claim 1, characterized in that it is marked ei c h η e t, .- that the control device (CSG) sequentially control signals (φ ) for the sense amplifier in an order pa that starts at the sense amplifiers that correspond to the memory cell columns., the physically close to the output terminals of the output Selector circuit are arranged, and then continues at the sense amplifiers, those memory cell columns which are remote from the output terminals of the selection circuit, so that their operation is started sequentially in an order that the sense amplifiers, which correspond to the memory cells located close to the output terminals of the selection circuit, begins and then continues at the sense amplifiers that correspond to the memory cell columns that are further away from the output terminals of the selection circuit. 3. Semiconductor memory according to claim 2, characterized in that
that the control device (CSG) has a control circuit for generating a sense amplifier control signal (φ) and a delay circuit which receives the sense amplifier control signal (φ) and controls pa signals produced, which alternately have different delay times, and that the delay circuit sequentially control signals φ on pa applies the sense amplifiers (SA) in an order starting with the sense amplifiers which the memory cell columns physically close to the output terminals of the selection circuit are positioned and advances to the sense amplifiers corresponding to the memory cell columns, which are physically removed from the output terminals of the selection circuit. 4. Semiconductor memory according to claim 3, characterized marked, that the delay circuit consists of a delay line having a number of output terminals and in parallel with the word line (W) is formed, and that the sense amplifier control signal {φ (is applied to this delay line from a side on which the selection circuit is arranged, so that the control signals alternately having different delay times, which are to be applied to the sense amplifiers , can be taken from the output terminals of the delay line. 5. Semiconductor memory according to claim 4, characterized marked t, - that the material of an electrically conductive layer which forms the delay line, essentially is the same material as that of the electrically conductive layer that forms the word lines (9, see above that the delay time of the delay line im * - 5 - is essentially the same as that of the word lines. 6. Integrated semiconductor memory according to claim 4, characterized in that that each sense amplifier (SA) has a differential amplifier circuit iQ., Q "; Q, Qj includes an input-output terminal with the corresponding Data line and the other of the input-output connections with a reference voltage (V £) is connected, and its operation through the control signal {φ ) is controlled, which at his pa Control connection is applied, and when a control signal is applied to the control connection, the differential amplifier circuit starts a positive feedback process so that the potential difference is amplified between the signal potential of the memory cell and the reference potential. 7. Semiconductor memory according to claim 6, characterized in that that the differential amplifier circuit consists of a first MOSFET (Q ₁ ) whose gate electrode is connected to one of the input-output terminals and whose drain electrode is connected to the other of the Input output terminals is connected, and a second MOSFET (Q ₂ ), the drain electrode of which is connected to one of the input output terminals and whose gate electrode is connected to the other of the input - output terminals, and that eir. Element with variable impedance is provided, the control electrode of which is connected to the control terminals and which is interposed between the boundary layer of the source electrodes of the first and the second MOSFET and the ground potential point of the circuit. 8. Semiconductor memory according to claim 7, characterized marked, that each memory cell has an address selection MOSFET (Q), whose gate electrode is connected to the word line (W), and in which one of the input Output electrodes to the data line CD) and the other of the input-output electrodes is connected to the data storage capacitor (C). 9. Semiconductor memory according to claim 8, characterized in that that precharge elements (PC) are provided to precharge a number of data lines (D, D), and that reset MOSFETs (Q ₁ 2 ~ Qi ö) are provided ^{on the} delay line are so that the variable impedance element in each of the sense amplifiers is in the high impedance state through the reset MOSFETs while the data lines are being precharged. 10. Semiconductor memory with an arrangement of bit lines laid together, characterized by:
a memory field with a number of memory cells (MC) and dummy cells (DMC) / die all have a select terminal and an input-output terminal, a number of word lines (W) to which the selection connections of the memory cells are connected are a number of dummy word lines (DW) to which the selection connections of the dummy cells are connected are and with a number of complementary data line pairs (D, D) to which the input-output connections of the memory cells and the dummy cells are connected and by a selection circuit (R-DCR) having a number of output terminals each connected to a End of a word line (W) and a dummy word line DW are connected and the selection signals for the Selection of one of the plurality of word lines and one of the dummy word lines accordingly the word line to be selected forms, by a number of sense amplifiers (SA) / each of which is connected with a pair of input-output terminals to the complementary data line pair (D, D) and to a control terminal and which the potential difference between the signal potential of the memory cell, MC) and the reference potential V. _{amplify f of} the blind cell (DMC), and by a control device CSG for applying control signals to the control terminals of the Sense amplifier £>. $, So these sense amplifiers too mutually start working at different times. 11. Semiconductor memory according to claim 10, characterized in that that the control device (CSG) sequentially produces control signals (φ J for the sense amplifier in pa an order that starts with those sense amplifiers that are physically closest to the Output terminals of the selection circuit lying complementary data line pairs are connected, and in the those sense amplifiers follow which are connected to the complementary Data line pairs are connected which are physically further away from those output terminals, so that the operation of the sense amplifiers is started in an order which begins with the sense amplifiers which are connected to the data line pairs physically closest to the output terminals and continues with the sense amplifiers, which are connected to ^the complementary data line pairs which are physically further removed from the output connections. 12. Semiconductor memory according to claim 11, characterized marked, that the control device CSG has a control circuit for forming a sense amplifier control signal (0) pa and a delay circuit that receives the sense amplifier control signals and control signals produced that have mutually different delay times, so that the delay circuit sequentially supplies the control signals to the sense amplifiers in an order that is identical to the sense amplifiers begins on the ones physically closest to the output terminals of the selection circuit Data line pairs are connected and continues with the sense amplifiers that are physically connected to the Complementary data line pairs further removed from the output connections are connected. 13. Semiconductor memory according to claim 12, characterized in that that the delay circuit consists of a delay line having a number of output terminals and which is formed in parallel with the word lines, and that the sense amplifier control signals applied to the delay line from the side on which the selection circuit R-DGR is arranged so that the mutually different delay times and to the sense amplifier Control signals applied to SA are taken from the output terminals of the delay line. 14. Semiconductor memory according to claim 13, characterized in that that the material of an electrically conductive layer forming the delay line is essentially is the same as the material of an electrically conductive layer that makes up the word lines forms so that the delay time of the delay line is substantially equal to the delay time the word lines is. 15. Semiconductor memory according to claim 13, characterized marked, that each of the sense amplifiers has a first MOSFET (Q-) has, the gate electrode of which is connected to one line (D) of the complementary data line pair and its drain electrode with the other line (D) of the complementary data line pair is connected, and has a second MOSFET whose gate electrode is connected to the other line (D) of the complementary data line pair is connected and its drain electrode to the one line (D) of the complementary data line pair is connected, and a variable impedance element has that between the boundary layer of the source electrodes of the first and the second MOSFET and the ground potential point of the circuit is arranged and its operation is controlled by the control signal will. 16. Semiconductor memory according to claim 15, characterized marked, - that the variable impedance element consists of a third MOSFET (QJ ₀ ; Q ₁ -j), of which one of the input-output electrodes is connected to the source electrode of the first and second MOSFETs (Q-] / Q ₂ ) and the other is connected Input-output electrode is connected to the JIassepotentialpunkt of the circuit and which receives the control signal [φ) at its gate electrode. pa 17. Semiconductor memory according to claim 16, characterized marked, that each memory cell has an address selection MOSFET (Q!, the gate electrode of which is connected to the word line and of which one of the input-output electrodes is connected to one of the complementary data line pairs (D , D), and a data storage capacitor (C) connected to the other of the input-output electrodes of the address selection MOSFET. 18. Semiconductor memory according to claim 17, characterized marked, that each of the word lines consists of an electrically conductive layer, which is an electrically conductive layer Polysilicon layer, and that the delay line consists of an electrically conductive layer which comprises an electrically conductive polysilicon layer. 19. Semiconductor memory according to claim 18, characterized marked, that the word line consists of an electrically conductive layer (8) which is an electrically conductive one Contains polysilicon layer which is integral with the gate electrode of the address selection MOSFET (Q) is formed within the memory cell and that the delay line consists of an electrical conductive layer, which comprises an electrically conductive polysilicon layer which is integrally is formed with the gate electrode of the third MOSFET within the sense amplifier. 20. Semiconductor memory according to claim 15, characterized marked, that the element with variable impedance has a fourth MOSFET, the conductivity of which on one is set relatively small value, and a fifth MOSFET, the conductivity of which is set to a is set relatively large value and which is made conductive more slowly than the fourth MOSFET and in parallel is connected to the fourth MOSFET. 21. Semiconductor memory according to claim 11, characterized in that a common Data line pair and a switch circuit is provided, the one pair from the number of complementary data line pairs with the common data line pair in accordance with the Selection circuit connects produced selection signal. 22. Semiconductor memory according to claim 21, characterized in that that the selection circuit (R-DCR) in a time division arrangement receives two sets of address signals from the outside and that they send the signals to the word lines, the dummy word lines and the switch circuit forms selection signals to be applied.