JPS6027119B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory that stores a large amount of information at high density.

Currently, semiconductor memories are frequently used as storage devices for electronic computers and the like.

When designing such a semiconductor memory, circuit design and pattern design are performed in units of blocks such as sense amplifiers and output circuits. i.e. the same circuit dimension,
A method of designing by arranging several blocks with a pattern is also used. However, for example, the output lines of the row decoder, ie, the row lines, are usually wired with polycrystalline silicon. Therefore, the resistance of polycrystalline silicon (approximately 3
Due to the capacitance of the row line and row line, there is a time difference in the time when the row line is specified between memory cells close to the row decoder and memory cells far from the row decoder. That is, the read time from the semiconductor memory becomes slower as the distance from the row decoder increases. Therefore, in such semiconductor memory,
Currently, the read speed is determined according to the bit that takes the longest time to read. This invention was made in view of the above-mentioned circumstances, and it improves the read speed of data appearing at each output terminal in accordance with the distance from the decoder, making it substantially the same overall, and simplifying memory read control. It is an object of the present invention to provide a semiconductor memory with improved overall reading speed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a read-only semiconductor memory with 8-bit parallel output, in which eight memory units 11 correspond to eight output terminals oo to 07.

~117. This memory unit 11. ~11
7 is a row and column decoder 12, 1 that performs addressing;
3 in the center, 4 memory units 11 on each side
. ~113 and 114~117, and as is clear from the figure, the decoders 12, 1
There are memory units 113 and 114 closest to 3, and it is set so that 11o and 1 17 are also present at the technique point. Memory units 11 of 4 each. ~11
3 and 114 to 117 are row lines CO. ~C's and C, . ~
It is configured with C and n in common. Furthermore, column decoder 1
Column designation lines Ro, ~Rom and R, . ~R,m is a memory unit 11. ~113 and 114 ~11? It is configured in common. The above unit is 11.

~117 have similar configurations, so
For example, the memory unit 113 will be explained in detail.
This memory unit 113 includes a memory block 143. This memory block 143 includes the n row lines CO. ~Con and m column lines L3, ~L3m are configured in a matrix, and memory cells 15, 15 and 15 are arranged at each intersection.
．． ~15 nm is arranged. These memory cells 1 5, . ~15 nm are composed of MOS transistors, each with a gate connected to the row line CO. ~C
"0" and "1" are stored depending on whether the drain is connected to -m of the corresponding column line L or not. Then, m column lines L taken out from the memory block 113
, ~-m are connected to the sources of MOS transistors T3, ~tm, each serving as a gate.

The gates of these transistors T3, -T3m are connected to the column designation line from the column decoder 13, and the drains are integrated at point d. Note that ~T3 of the above transistor T
m forms a column gate circuit 163, and the potential at point d is sensed by a sense amplifier 173 and outputted from the output terminal 03 as 1-bit information of "1" or "0" via the output circuit 183. ing. That is, in the memory unit 113 configured in this way, the row decoder 11 and the column decoder 13, for example,
O. When an IJ level signal is supplied to the row line CO. and the column designation line, the row line CO. and the column line - are designated, and the memory cells 15, . are in a selected state.

In this case, the drain of this memory cell 1511 is connected to the column line -
, so if the information stored in this memory cell is "0", "0" information appears at point d, and "0" is output via the sense amplifier 173 and output circuit 183.
The information will be output from the output terminal 03 as information.
Note that the sense amplifier 173 and the output circuit 183
The output section 193 is configured from the following. In this way the memory unit 11.

~117 Since each of these is configured, 8-bit parallel information can be output by addressing with the row decoder 12 and column decoder 13. In a semiconductor memory configured as described above, if each memory unit has the same configuration conditions, for example, the row line CO. and C, .
When specifying the memory cells near the row decoder 12, for example, 15, . , and in the farthest memory cell, for example 15M, the row line CO. There is a time difference in the time it takes to be specified.

Therefore, as shown in the solid line in Fig. 2, each output terminal oo
There is a time difference when the data of the memory cell appears at ~08. That is, as the distance from the row decoder 2 increases, the time at which data appears at its output terminal becomes delayed, so that, for example, 8-bit information is not output synchronously. In view of the above points, the present invention is intended to eliminate the time difference and extract, for example, 8-bit read information regardless of the distance difference from the row decoder and the column decoder.

That is, each memory unit 11. Memory blocks 14o to 147 and sense amplifiers 170 to 117
177, output circuit 18. In at least one set of circuits 1 to 187, the response is set to be faster depending on the distance from the decoder. For example, the channel width and channel length of the transistors constituting these circuits are set to
2 and each output terminal oo~0
The purpose is to make the reading times of the data appearing in 7 coincide with each other, as shown by the broken line in FIG. 2, for example. Specifically, the memory blocks 14 respectively correspond to the output terminals oo to 07. The dimensions (capabilities) of the transistors of the memory cells constituting the memory cells 147 to 147 are set as shown in Table 1, for example, depending on the position with respect to the row decoder 12. Here, the dimensions (capacity) of the transistors constituting the memory cell are as shown in FIG. It is determined from the channel medium W and the channel length L, and the W/L value is shown in the table in microns. That is, as the distance from the row decoder 12 increases, the dimensions (capabilities) of the transistors constituting the memory cells in the memory block change. Table 1 Unit micron (channel length/channel length) With this configuration, the further away from the row decoder 12 the larger the dimensions of the transistors constituting the memory cell become. At the latest, a large memory cell current can flow.

Therefore, the charging/discharging time of the column line, that is, the response time can be shortened, and data in a designated memory cell is led to the sense amplifier further. That is, by changing the dimensions (capacity) of the transistors constituting the memory cell, the stored data in the selected memory cell will appear at the output terminals oo~07, for example, as shown by the broken line in FIG. It will be read out at a faster speed. Note that in the above embodiment, the dimensions of the transistors constituting the memory cells are changed for each memory block, but this also means that even within the same memory block, the dimensions of the transistors on the side closer to the row decoder 12 and the side farther away from the row decoder 12 are different. Of course, the size may be changed.

However, within the same memory block, the response time difference between the two ends is relatively small, so the purpose of the present invention can be fully achieved by setting the size of the transistors constituting the memory cells for each memory block. Further, in the above embodiment, the present invention is applied to a read-only semiconductor memory, but it is of course applicable to a RAM (Random Access Memory) as well.

Also, a memory block 14.

-147 are all configured under the same configuration conditions, and are output circuits 18.
.about.187 may be similarly implemented by changing the size of the transistors constituting the transistors. FIG. 4 shows one of the output circuits 18o to 187, and the signal CS is a chip selection signal determined by a CPU (not shown) or the like and stored in this memory. This signal C
For example, when S is at the "0" level, the transistors 20 and 21
is turned off, and the inverted signal CS turns transistors 22 and 23 on. That is, both output transistors 24 and 25 are turned off, and the output is placed in a floating state. In this case, regardless of the signal level state of the signal S from the sense amplifier, it will not be output, indicating that the memory is in a non-selected state. Further, when the chip selection signal CS is at the "1" level, the transistors 20 and 21 are turned on, and the inverter circuit 1 is made up of transistors 26 and 27, and the inverter circuit 12 is made up of transistors 28 and 29. becomes operational.

In this state, the signal S from the sense amplifier is "1" or "
0'' logic level state, transistors 30,3
1, and further transistor 32.
, 33, respectively. The inverter circuit also receives a signal X which is an inversion of the signal S from each L, and a signal X having the same logic as the signal S.
2 controls the gates of transistors 27, 28 and 26, 29, and outputs the output signals Y of inverter circuits 1 and 12.
, , determine the logical state of Y2. And each output circuit 18 configured in this way. ~187 The size of each corresponding transistor in the output circuit 18 is, for example, as shown in Table 2. ~187 Each of them is made to differ sequentially. That is, the further away from the row decoder 12, ie, the memory blocks 143→14. and 1
The size of the transistors constituting the output circuits 18o to 187 that output the stored information in the memory block is increased in the order of 44→147, thereby speeding up the operation of the output circuits. Therefore, as shown by the broken line in FIG. 2, the data appearing at each output terminal oo-07 can be made equal. Table 2 Unit: Micron (Channel Medium/Channel Length) Table 2 shows all the main transistors that make up the output circuit, but in reality, at least one of them is used to match the response speed. The required range of transistors may be set according to the relationship shown in Table 2.

Furthermore, sense amplifier 17. The response time difference can also be corrected by changing the dimensions of the transistors constituting .about.177. FIG. 5 shows the sense amplifier 17. ~177 is extracted and shown. That is, when the memory cell signal outputted through the column gate circuit described above is "0", the column line is released through the memory cell. Then, the signal S becomes the "0" level and is transmitted to the output circuit. When the data from the time series gate circuit falls below a certain potential level, the outputs of the inverter circuits become "1" and the gate potentials of the transistors 42 and 43 rise. This increases the current supply capability of transistor 42, preventing the column line from going all the way to ground potential and holding the column line at some level of logic "0" level. On the other hand, the information stored in the memory cell is "1"
”, the column line is charged by the power supply VC through transistors 44, 43 and transistor 42. When this time column line reaches a certain potential level or higher, the output of the inverter circuit becomes "0", and the column line is prevented from rising above a certain potential and is kept at a constant potential. At this time, transistor 4
3 becomes a non-conducting state, and the potential of the signal S increases to the fin source NC. Such a sense amplifier maintains the column line potential near the threshold voltage of the transistor 41, and the column line potential rises and falls around this threshold voltage. In addition, the output of the inverter circuits does not completely reach the ground level or the power supply VC potential, but for example, when the power supply VC = 5V, the output is 2V to 4V.
The voltage rises and falls between the lines depending on the column line potential. And each sense amplifier 17. The sizes of the corresponding transistors constituting .about.177 are set as shown in Table 3, for example. Table 3 Unit: Micron (channel length), i.e.
As the memory block moves away from row decoder 2,
The dimensions (channel middle/channel length) of the transistors constituting the sense amplifier are increased.

Specifically, when looking at sense amplifiers 173 and 17o,
As shown in FIG. 5, they have similar circuit configurations, so for example, the size of the corresponding transistor 40 in the sense amplifier 173 is 7/14 in the sense amplifier 17. So 13
/14. Further, an example will be shown in which both the dimensions of the transistors forming the memory cell and the dimensions of the transistors forming the sense amplifier are changed.

When the transistors configuring the memory cell shown in Table 1 are used, the transistors configuring the sense amplifier are:
For example, the dimensions shown in Table 4 are used. This is connected to the memory cell through a column gate circuit, transistors 44, 43, and transistor 4 constituting a sense amplifier.
Since transistor 2 forms a kind of inverter circuit, transistor 4, which can be considered as a load transistor of the inverter circuit, is
By changing the dimensions of the memory block 4, 43 and the transistor 42, the charging and discharging time of the column line is made shorter in the memory block 14o than in the memory block 143, for example. table
4. As described below, according to the present invention, it is possible to provide a semiconductor memory in which the reading speed of data appearing at each output terminal is made substantially the same and the memory reading speed is improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a diagram comparing and showing the difference in time at which data is read to each output terminal in the semiconductor memory of the present invention.
FIG. 3 is a plan view of a general MOS transistor, FIG. 4 is a circuit diagram of an output circuit in the semiconductor memory, and FIG. 5 is a circuit diagram of a sense amplifier. 11o-117...Memory unit, 14. ~147...Memory block, 15...Memory cell, 1
6. ~167...Column gate circuit, 17. ~17
7...Sense amplifier, 18. ~187...Output circuit, 1
9. ~197...Output section. Figure 3 Figure 5 Rudder Figure 2 Figure 4

Claims (1)

[Scope of Claims] 1. A row line, a row decoder that selects the row line, a memory cell that is selectively driven by the row decoder and the row line, and a column line that receives data from the memory cell.
It includes a column decoder that selects this column line, and an output section that detects and outputs data on the selected column line, so that the response speed for outputting the data of the memory cell changes depending on the distance from the row decoder. A semiconductor memory comprising: 2 The dimensions of the transistor constituting the memory cell are:
2. The semiconductor memory according to claim 1, wherein the distance is set according to the distance from the row decoder. 3. The output section includes a sense amplifier that detects information from the memory cell, and the dimensions of a transistor used in the sense amplifier are set according to the distance from the row decoder that drives the memory cell. A semiconductor memory according to claim 1. 4. The output section includes an output circuit that outputs information from the memory cell, and the dimensions of transistors constituting the output circuit are set according to the distance from the row decoder that drives the memory cell. A semiconductor memory according to claim 1, characterized in that: