GB826109A - Improvements in or relating to checking circuits for ring counters and the like - Google Patents

Improvements in or relating to checking circuits for ring counters and the like

Info

Publication number
GB826109A
GB826109A GB7354/58A GB735458A GB826109A GB 826109 A GB826109 A GB 826109A GB 7354/58 A GB7354/58 A GB 7354/58A GB 735458 A GB735458 A GB 735458A GB 826109 A GB826109 A GB 826109A
Authority
GB
United Kingdom
Prior art keywords
ring
trigger
triggers
gate
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB7354/58A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB826109A publication Critical patent/GB826109A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/08Output circuits

Landscapes

  • Control Of Direct Current Motors (AREA)

Abstract

826,109. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 7, 1958 [March 8, 1957], No. 7354/58. Class 106 (1). An error detecting circuit, upper half Fig. 1, is described for detecting the incorrect operation of a ring of triggers 16a-16n along which an " on " condition is advanced by ring drive pulses applied to a terminal 36. In operation after each ring drive pulse a sample and reset pulse is applied to a terminal 68 which tests the error detecting circuit to see whether an error has been detected and at the same time resets it for detecting further errors. The circuit comprises a first " or " circuit 42 which receives signals from the odd triggers of the ring (i.e. triggers 16a, 16c, 16e, &c.) and a second " or " circuit 44 which receives signals from the even triggers. Outputs from these " or circuits pass, inter alia, direct to an " and " gate 58 which is thus opened when both an odd and an even trigger are " on " simultaneously. Thus if this should occur after a ring drive pulse, the next sample and reset pulse will pass through a gate 66 to give an error signal. However, should two even triggers or two odd triggers both be " on " simultaneously this will not be detected by " and " gate 58, and the two " on " conditions will advance along the chain until the last trigger of the chain trigger 16n goes " on." The fact that another trigger is " on " together with trigger 16n will then be detected by an " and " gate 62 which has for one of its inputs the output of trigger 16n and for its other the mixed outputs of all the other triggers in the chain. Thus the next sample and reset pulse will produce an error signal. The error detecting circuit also includes a trigger 52 which is reset by each sample and reset pulses and whose condition is changed over each time a trigger in the ring goes " on." If the ring is functioning correctly after each ring advance pulse one trigger will go " on " thereby turning trigger 52 " on " (left-hand output low) and a gate 54, which also receives a " ring op " signal when the ring is operating, is closed. However, if after a ring advance pulse the " on " condition in the ring advance two positions then the trigger will first be turned " on and then turned " off " and this gate 54 will be open and the next sample and reset pulse will produce an error signal. If the ring is not operating, that is if every trigger thereof should be " off " then a " no ring op " signal is present and should a trigger of the ring go " on " (because of a spurious pulse) trigger 52 will be turned " on " to open a gate 56. A subsequent sample and reset pulse will therefore produce an error signal. The ring is advanced by negative pulses on a line 20 which pass through gates 18a to 18n to turn " on " one of triggers 16a to 16n and reset the immediate preceding trigger. With a switch 40 in the position shown the ring is open but it can be closed by operation of the switch.
GB7354/58A 1957-03-08 1958-03-07 Improvements in or relating to checking circuits for ring counters and the like Expired GB826109A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US826109XA 1957-03-08 1957-03-08

Publications (1)

Publication Number Publication Date
GB826109A true GB826109A (en) 1959-12-23

Family

ID=22172242

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7354/58A Expired GB826109A (en) 1957-03-08 1958-03-07 Improvements in or relating to checking circuits for ring counters and the like

Country Status (1)

Country Link
GB (1) GB826109A (en)

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