GB771463A - Improvements in and relating to electric pulse counting and calculating apparatus - Google Patents

Abstract

771,463. Digital electric calculating apparatus. OLIVETTI & C., SOC. PER AZIONI, ING., C. Feb. 1, 1955, [Feb. 3, 1954], No..2928/55. Addition to 731,140. Class 106 (1). In the calculating apparatus described and claimed in the parent Specification, upon the generation of an impulse representing a unit to be added into the accumulator the commutating means is conditioned to commutate two-condition elements sequentially presented thereto from a certain first condition to a second condition, but this conditioning is discontinued after an element initially in the first condition has been detected by sensing means and has been commutated. At the beginning of an accumulator cycle, when the magnetic read/write head 3 is at the beginning of the first sub-order IR1 of the input register, a signal d (i.e. denomination clock pulse) sets flip-flops 17, 25 and 31 to state I. Subsequently, as long as the head 3 reads negative elements in IR1, output 10 is energized without effect. During this period each m signal (i.e. digit clock pulse) passes through " AND " gates 27 and 29 (in the case of Addition) and energizes negatively the " write " coil 11 of head 3. When the first positive element is sensed by the head 3 an output on line 9, after passing a delay unit 35, passes through a gate 22 to set flip-flops 21 and 25 to state II. This' occurs after the element giving rise to the signal has been changed to a negative condition by coil 11; subsequent m signals are blocked at the gate 27 until a signal r at the beginning of the first sub-order AR1 of the accumulator resets the flip-flop 25 to state I. The m signals now pass gates 27 and 28 to cause positive signals at the writing coil 11. When the first negative element is sensed in the sub-order AR1 the coil changes it to a positive condition and an output signal on line 10 passes through gate 19 to set the flip-flop 25 to state II, and reset the flip-flop 21 to state I, thus, once again, blocking subsequent m signals. The same process is followed in denomination D2, and so on. If during a sub-order IRn there are no positive elements to cause the flip-flop 25 to be set to state II, the signal r passes gates 23 and 20 to set the flip-flop 25 to state II, and this prevents m signals from energizing the writing coil 11 during the entire sub-order ARn. Similarly, if during a sub-order ARn the flip-flop 25 is not set to state II because there are no negative elements present, the flip-flop 21 remains in state II and the signal d, passing gates 24 and 20, sets the flip-flop 25 to state II to prevent m signals from being effective during the entire next sub-order IR(n+1). Since the latter case requires a tens transfer, the signal d also sets a flip-flop 31 to state II whereby each m signal now energizes the following head 4 which returns all the elements in ARn to the negative condition. Moreover, as the head 3 reaches the next following sub-order AR(n+ 1), the first negative element (if any) will be changed over to a positive condition as described above. Subtraction is performed when the switches 18, 30 and 34 are changed over, negative remainders and " fugitive one correction being provided for.