GB771388A - Improvements in and relating to digital computing apparatus - Google Patents

Abstract

771,388. Digital electric calculating apparatus. OLIVETTI & C., SOC. PER AZIONI, ING., C. Feb. 1, 1955 [Feb. 3, 1954], No. 2929/55. Class 106 (1). Digital computing apparatus comprising a cyclically moving accumulator having a plurality of impulse registering elements each commutatable to assume either of two stabe conditions, means for sensing the elements, and means for commutating them to enter impulses into the accumulator, is characterized in that the commutating means are controlled by an intermediary multi-stable-state device adapted to store impulses and to operate the commutating means a corresponding number of times during a single accumulator cycle. In the described embodiment sections of a track a, Fig. 3, on a rotating magnetic drum are allocated to units (D1) tens (D2) &c., each section comprising sub-sections forming an input register IR1, 2, &c., accumulating register AR1, 2, &c., and auxiliary register HR1, 2, &c., and each containing ten elemental areas which can be magnetized positively to represent a decimal digit, erasure being accomplished by magnetizing negatively. A read/write head 3, Fig. 2, and a write head 4, spaced ten elements behind, move relatively to the track a in a direction from left to right, and, as shown with switches 19, 32, 33, 35 set for addition, positively magnetized elements in sub-section IR1 detected by the winding 12 of head 3 give rise to impulses which pass through OR gate 20, AND gate 26, and OR gate 27 to a scale-of-ten counter 28 which may be a multi-cathode gas-discharge tube. The curve b, Fig. 3, represents the state of this counter during an example of addition (45 + 47 = 92); c represents the final condition of the track a. The stepping on of the counter 28 is continued as the winding 12 detects positive elements in sub-section AR1 until the tenth impulse is received, and during this phase the winding 18 of the following head 4 writes negative erasing signals into all the elements of IR1. Negative signals are also developed (after a slight delay) in winding 14 of head 3 to erase the positive signals counted by the device 28, but when the latter returns to zero on receiving the tenth impulse, an output signal passes through an AND gate 30 to reverse a flip-flop 25 which stops the supply of erasing signals to winding 14 at a gate 36 and also closes gate 26 to prevent further impulses from reaching the counter 28. Thus any further positive elements in the sub-section AR1 (two in the example shown) remain undisturbed. Carry into the next higher denomination IR2 is performed when a control signal d, which appears on terminal 9 as the head 3 enters the sub-section IR2, is gated through 31 and 27 to step on the counter 28 before the flip-flop 25 is returned to state N by a slightly delayed version of the same signal d. Detection of more positive elements in IR2 and AR2 causes further entry of impulses into the counter 28 which, in the example shown, does not reach the full count of ten before HR2 is reached. The winding 18 of head 4 erases all positive elements in IR2 and the winding 13 of head 3 erases the counted elements in RA2, as before. As the counter receives the tenth impulse while the head 3 is passing HR2 (phase III), the flip-flop 24 is set to state C and thiscloses gate 36 preventing any further erasures by the winding 14, closes gate 38 to render the negative writing coil 18 inoperative, and opens a gate 37 to supply signals to the positive coil 17 so that positive elements are written into AR2, the number (nine in the example) depending on the position reached by the head 4 when the counter 28 is zeroized. Subtraction of the amount registered in IR1, 2, &c., from that registered in AR1, 2, &c., is performed when the ganged switches 19, 32, 33, 35 are moved to the S position. There is provision for a negative result and " fugitive one " correction. Other forms of registering means besides magnetic may be used. Specification 731,140 is referred to.