GB760967A - Electrical signal storage systems - Google Patents

Abstract

760,967. Electric digital-data-storage apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Feb. 4, 1955 [Feb. 12, 1954], No. 4210/54. Class 106 (1). An electronic arrangement for transferring signals from a low-speed store to a high-speed store in which the high-speed store stores a serial train of signals in such a manner that each signal is made repetitively available at times which are separated by a given repetition period and in which the low-speed store produces signal units at a maximum rate which is less than the repetition rate of the high-speed store, comprises a signal transfer path from the low-speed store to the high-speed store, a timing device for controlling the transfer path and which when operating normally produces at basic time intervals timing pulses for opening the transfer path to permit the passage of signal units, said basic time intervals being a whole number including one times the said given repetition period of the high-speed store, and means for modifying the normal operation of the timing device whereby the basic time interval preceding the next timing pulse which occurs after the first passage of a signal unit through the transfer path is changed by the time period allocated to a signal unit in the high-speed store, the greater one of the modified and basic time intervals of the timing device being arranged to be less than the minimum time interval between successive signal units produced by the lowspeed store. As described, data stored in four parallel tracks on a magnetic tape T is read and transferred to a one-word mercury delay line DL<SP>2</SP>. As each signal unit on the tape is read by heads H<SP>1</SP>, H<SP>2</SP>, H<SP>3</SP>, H<SP>4</SP>, it is registered in staticizors S<SP>1</SP>, S<SP>2</SP>, S<SP>3</SP>, S<SP>4</SP>, under control of a clock pulse from the tape, and a trigger T<SP>1</SP> is set " on." In a three-word delay line DL<SP>1</SP>, constituting the timing device, one pulse is circulating. Upon the first arrival of the pulse at the exit of the delay line DL<SP>1</SP> immediately after the setting " on " of the trigger T<SP>1</SP>, the trigger T<SP>1</SP> is set " off," the pulse is delayed four units by a delay D<SP>5</SP> before it returns to the delay line, and by virtue of unit delays D<SP>1</SP>, D2, D<SP>3</SP>, the signal unit staticized is entered serially into the delay line DL<SP>2</SP>. Upon the second arrival of the pulse at the exit of the delay line DL<SP>1</SP>, if a second signal unit has not yet been staticized, and therefore if trigger T<SP>1</SP> is still " off," the pulse passes directly back to the delay line and the first signal unit is re-written in the same place as before in the delay line DL<SP>2</SP>; if, however, a second signal unit has been staticized, i.e. if trigger T<SP>1</SP> is " on," then the pulse is delayed by four units before it returns to the delay line DL<SP>1</SP> and the second signal unit is entered serially into the delay line DL<SP>2</SP> immediately behind the first signal unit. This process continues until the pulse in delay line DL<SP>1</SP> has been delayed by eight signal unit periods when a trigger T<SP>2</SP> is set " on " and the contents of delay line DL<SP>2</SP> discharged to a computer. Specification 717,114 is referred to.