GB624440A - Improvements in or relating to pulse delaying circuit arrangements - Google Patents
Improvements in or relating to pulse delaying circuit arrangementsInfo
- Publication number
- GB624440A GB624440A GB22223/46A GB2222346A GB624440A GB 624440 A GB624440 A GB 624440A GB 22223/46 A GB22223/46 A GB 22223/46A GB 2222346 A GB2222346 A GB 2222346A GB 624440 A GB624440 A GB 624440A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- pulses
- octode
- stage
- desired delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
- Electrotherapy Devices (AREA)
- Dental Tools And Instruments Or Auxiliary Dental Instruments (AREA)
Abstract
624,440. Pulse delaying circuits. SADIRCARPENTIER. July 25, 1946, No. 22223. Convention date, Feb. 13, 1945. [Class 40 (vi)] In a pulse delaying circuit, pulses to be delayed from a source 1 synchronize a pulse generator 2 whose repetition period is a factor of the, desired delay and the repetition period of the original pulse, and also cause a resonant circuit 5 damped by a rectifier to ring and produce a half cycle of oscillation which is equal in period to the desired delay and thus blocks an octode 8 to which it is applied, together with the pulses from generator 2, until the desired delay time has elapsed. The first of the string of pulses which now appears at the anode of octode 8 is selected by passing the output through a phase reversing stage 13 and a stage 14 in which the first pulse charges a capacitor 17 in the cathode circuit to a peak voltage, rendering the stage insensitive to further pulses until the capacitor discharges through a parallel resistor 1, the time constant being equal to the original pulse repetition period. The output is taken off through a differentiating capacitor 18. A pentode or hexode may be substituted for the octode 8.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR624440X | 1945-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB624440A true GB624440A (en) | 1949-06-08 |
Family
ID=8987102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB22223/46A Expired GB624440A (en) | 1945-02-13 | 1946-07-25 | Improvements in or relating to pulse delaying circuit arrangements |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR961769A (en) |
GB (1) | GB624440A (en) |
-
0
- FR FR961769D patent/FR961769A/fr not_active Expired
-
1946
- 1946-07-25 GB GB22223/46A patent/GB624440A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR961769A (en) | 1950-05-20 |
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