GB2589951A - Error-controllable ultra-wideband compact active power divider - Google Patents

Error-controllable ultra-wideband compact active power divider Download PDF

Info

Publication number
GB2589951A
GB2589951A GB2013539.8A GB202013539A GB2589951A GB 2589951 A GB2589951 A GB 2589951A GB 202013539 A GB202013539 A GB 202013539A GB 2589951 A GB2589951 A GB 2589951A
Authority
GB
United Kingdom
Prior art keywords
resistor
output
output stage
stage circuit
nmos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB2013539.8A
Other versions
GB2589951B (en
GB202013539D0 (en
Inventor
Ma Jianguo
Zhou Shaohua
Yang Shenghui
Xu Jiangtao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Publication of GB202013539D0 publication Critical patent/GB202013539D0/en
Publication of GB2589951A publication Critical patent/GB2589951A/en
Application granted granted Critical
Publication of GB2589951B publication Critical patent/GB2589951B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/32—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/36—Networks for connecting several sources or loads, working on the same frequency band, to a common load or source
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/06—Frequency selective two-port networks comprising means for compensation of loss
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

An error-controllable ultra-wideband compact active power divider comprises a pre-output stage circuit and first and second output stage circuits. The pre-output stage circuit includes a first NMOS transistor M1, an input port connected to radio frequency (RF) signal input IN, and two output ports OUT1, OUT2; the first and second output stage circuits respectively include second and third NMOS transistors M2, M3, and each have one input port and one output port OUT3, OUT4. The input ports of the first and second output stages are each connected to a different one of the output ports of the pre-output stage, and the output ports of the first and second output stages constitute equal power division output ends of the active power divider. Additionally, the first and second output stage circuits are each provided with a load balancing adjustable device for fine-tuning, or calibrating, the circuit. The adjustable device may be an adjustable resistor R, adjustable capacitor C, or adjustable resistor and adjustable capacitor connected in parallel. The active power divider is applicable to multiple frequency bands and may be used in a communication system where small chip area, and high amplitude and phase consistency, are advantageous.

Description

ERROR-CONTROLLABLE ULTRA-WIDEBAND COMPACT ACTIVE POWER DIVIDER
Technical field
The present invention relates to an active power divider. In particular, it relates to an error-controllable ultra-wideband compact active power divider.
Technical background
Power dividers are basic devices of microwave systems and circuits, and are widely used in microwave and millimeter wave transceiver systems. The basic power dividers are mainly T-junction power dividers, Wilkinson power dividers, and Bagley power dividers. The T-junction power divider has a simple structure, but the problem of poor port isolation limits its further application. Wilkinson power distribution technology is based on a quarter-wavelength impedance transformation. It has advantages such as a simple structure, excellent port isolation, and highly consistent amplitude and phase. However, its area is not compact enough, and a quarter-wavelength structure will occupy a lot of chip area at a lower frequency band, and it is not compact enough even in the millimeter wave frequency band.
In a millimeter-wave array type system, a large-scale power distribution network is required to realize the cooperation operations of multiple array elements. If an area of a single power divider circuit is too large, it is difficult to expand the design on a large scale, which greatly limits the system cost. At present, the ultra-wideband power divider circuit designed with a passive structure is still limited by the passive structure itself, that is, it depends on the process size and operating frequency band. In addition, the passive structure brings more losses in high-frequency applications. Moreover, in large-scale applications, the losses are superimposed, and a large amount of power consumption needs to be sacrificed to compensate. Therefore, designing an error-controllable ultra-wideband compact active power divider integrated circuit has practical application value.
Summary of the invention
A technical problem to be solved by the present invention is to provide an error-controllable ultra-wideband compact active power divider, having ultra-wideband, compact and active characteristics.
A technical solution adopted by the present invention is: an error-controllable ict ultra-wideband compact active power divider, comprising a pre-output stage circuit composed of a first NMOS transistor and having one input port and two pre-output ports, and a first output stage circuit and a second output stage circuit correspondingly composed of a second NMOS transistor and a third NMOS transistor, respectively, and having one input pod and one output port, wherein the input port of the pre-output stage circuit is connected to a RF signal input IN; the input port of the first output stage circuit is connected to one pre-output port of the pre-output stage circuit; the input port of the second output stage circuit is connected to another pre-output pod of the pre-output stage circuit; the output ports of the first output stage circuit and the second output stage circuit constitute two power equal division output ends of the error-controllable ultra-wideband compact active power divider; and the first output stage circuit and the second output stage circuit each are provided with a load balancing adjustable device for fine-tuning the circuit.
The pre-output stage circuit is as follows: a gate of the first NMOS transistor is connected to the RF signal input IN, a drain of the first NMOS transistor constitutes a first pre-output port OUT1, a source constitutes a second pre-output port OUT2, the drain is further connected to a power source VDD through a first resistor RL1, the source is further grounded through a second resistor RL2, and the first resistor RL1 and the second resistor RL2 has the same resistance value.
The first output stage circuit is as follows: a gate of the second NMOS transistor is connected to the first pre-output port OUT1 of the pre-output stage circuit, a source of the second NMOS transistor is an output port and constitutes one power equal division output end OUT3 of the error-controllable ultra-wideband compact active power divider, the source is further grounded through a fourth resistor R4, a drain of the second NMOS transistor is connected to a power source VDD through a third resistor R3, the drain is further grounded through one load balancing adjustable device, and the third resistor RL3 and the fourth resistor RL4 have the same resistance value.
The second output stage circuit is as follows: a gate of the third NMOS transistor is connected to a second pre-output pod OUT2 of the pre-output stage circuit, a drain of the third NMOS transistor is an output pod and constitutes one power equal division output end OUT4 of the error-controllable ultra-wideband compact active power divider, the drain is further connected to a power source VDD through a fifth resistor R5, a source of the third NMOS transistor is grounded through a sixth resistor R6, and the source is further grounded through one load balancing adjustable device, and the fifth resistor RL5 and the sixth resistor RL6 have the same resistance value.
The load balancing adjustable device is an adjustable resistor.
The load balancing adjustable device is an adjustable capacitor.
The load balancing adjustable device is composed of an adjustable resistor and an adjustable capacitor connected in parallel.
A first resistor RL1 and a second resistor RL2 with which a drain and a source of the first NMOS transistor are connected in series, a third resistor RL3 and a fourth resistor RL4 with which a drain and a source of the second NMOS transistor are connected in series, and a fifth resistor RL5 and a sixth resistor RL6 with which a drain and a source of the third NMOS transistor are connected in series, have the same resistance value.
An error-controllable ultra-wideband compact active power divider according to the present invention has ultra-wideband, compact, active and error-controllable characteristics, and is applicable to multiple frequency bands and error-controllable.
The present invention has the following beneficial effects: (1) The circuit is implemented with an active structure, avoiding the inherent loss of 3dB per stage due to equal division of power, which can maintain a low loss and even generate a partial gain.
(2) The circuit main body is composed of a transistor and a small resistor, and thus the structure is compact and the cost is reduced.
(3) The adjustable device is introduced, the circuit balance degree is adjusted by the adjustable resistor and/or the variable capacitor, and symmetrical circuit topology is added, so that the two output ends with the same amplitude and the same phase of output power are achieved, and the error can be controlled.
Brief description of the drawings
Fig 1 is a schematic circuit diagram of an error-controllable ultra-wideband compact active power divider of the present invention.
Detailed description of the embodiments
An error-controllable ultra-wideband compact active power divider of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings. The exemplary embodiments of the present invention and the description thereof are only used to explain the present invention, and are not intended to limit the present invention.
The error-controllable ultra-wideband compact active power divider of the present invention can be implemented in a CMOS process. Due to its highly symmetrical structure, the circuit has low sensitivity with respect to the process.
As shown in Fig. 1, an error-controllable ultra-wideband compact active power divider of the present invention includes a pre-output stage circuit composed of a first NMOS transistor M1 and having one input port and two pre-output ports, and a first output stage circuit and a second output stage circuit correspondingly composed of a second NMOS transistor M2 and a third NMOS transistor M3, respectively, and having one input port and one output port. Herein, the input port of the pre-output stage circuit is connected to a RE signal input IN; the input port of the first output stage circuit is connected to one pre-output port of the pre-output stage circuit; the input port of the second output stage circuit is connected to another pre-output port of the pre-output stage circuit; the output ports of the first output stage circuit and the second output stage circuit constitute two power equal division output ends of the error-controllable ultra-wideband compact active power it) divider; and the first output stage circuit and the second output stage circuit each are provided with a load balancing adjustable device for fine-tuning the circuit.
The pre-output stage circuit is as follows: a gate of the first NMOS transistor M1 is connected to the RF signal input IN, a drain of the first NMOS transistor M1 constitutes a first pre-output port OUT1, a source constitutes a second pre-output port OUT2, the drain is further connected to a power source VDD through a first resistor RL1, the source is further grounded through a second resistor RL2, and the first resistor RL1 and the second resistor RL2 has the same resistance value.
The first output stage circuit is as follows: a gate of the second NMOS transistor M2 is connected to the first pre-output port OUT1 of the pre-output stage circuit, a source of the second NMOS transistor M2 is an output port and constitutes one power equal division output end OUT3 of the error-controllable ultra-wideband compact active power divider, the source is further grounded through a fourth resistor R4, a drain of the second NMOS transistor M2 is connected to a power source VDD through a third resistor R3, the drain is further grounded through one load balancing adjustable device, and the third resistor RL3 and the fourth resistor RL4 have the same resistance value.
The second output stage circuit is as follows: a gate of the third NMOS transistor M3 is connected to a second pre-output port OUT2 of the pre-output stage circuit, a drain of the third NMOS transistor M3 is an output port and constitutes one power equal division output end OUT4 of the error-controllable ultra-wideband compact active power divider, the drain is further connected to a power source VDD through a fifth resistor R5, a source of the third NMOS transistor M3 is grounded through a sixth resistor R6, and the source is grounded through one load balancing adjustable device, and the fifth resistor RL5 and the sixth resistor RL6 have the same resistance value The first resistor RL1 and the second resistor RL2 with which the drain and the source of the first NMOS transistor M1 are connected in series, the third resistor RL3 and the fourth resistor RL4 with which the drain and the source of the second NMOS transistor M2 are connected in series, and the fifth resistor RL5 and the sixth resistor RL6 with which the drain and the source of the third NMOS transistor M3 are connected in series, have the same resistance value.
The load balancing adjustable device is an adjustable resistor R. Alternatively, the load balancing adjustable device is an adjustable capacitor C. Alternatively, the load balancing adjustable device is composed of an adjustable resistor R and an adjustable capacitor C connected in parallel. Since the circuit structure of the present invention is symmetrical, the circuit can be fine-tuned with a load balancing adjustable device, so that equal-amplitude and in-phase equal division of the input signal can be achieved; after deviations in the operating state of the circuit can be calibrated through the load balancing adjustable device, the error can be controlled; the circuit main body of the present invention is composed of a transistor and a small resistor, and thus the structure is compact; and at the same time, the active circuit also causes the circuit to maintain a low loss (or provide a certain gain).

Claims (8)

  1. Claims 1. An error-controllable ultra-wideband compact active power divider, characterized in that it comprises a pre-output stage circuit composed of a first NMOS transistor (M1) and having one input port and two pre-output ports, and a first output stage circuit and a second output stage circuit correspondingly composed of a second NMOS transistor (M2) and a third NMOS transistor (M3), respectively, and having one input port and one output port, wherein the input port of the pre-output stage circuit is connected to a RF signal input IN; the input port of the first output stage to circuit is connected to one pre-output port of the pre-output stage circuit; the input port of the second output stage circuit is connected to another pre-output port of the pre-output stage circuit; the output ports of the first output stage circuit and the second output stage circuit constitute two power equal division output ends of the error-controllable ultra-wideband compact active power divider; and the first output stage circuit and the second output stage circuit each are provided with a load balancing adjustable device for fine-tuning the circuit.
  2. 2. The error-controllable ultra-wideband compact active power divider according to claim 1, characterized in that the pre-output stage circuit is as follows: a gate of the first NMOS transistor (M1) is connected to the RF signal input IN, a drain of the first NMOS transistor (M1) constitutes a first pre-output port OUT1, a source constitutes a second pre-output port OUT2, the drain is further connected to a power source VDD through a first resistor RL1, the source is further grounded through a second resistor RL2, and the first resistor RL1 and the second resistor RL2 has the same resistance value.
  3. 3. The error-controllable ultra-wideband compact active power divider according to claim 1, characterized in that the first output stage circuit is as follows: a gate of the second NMOS transistor (M2) is connected to the first pre-output port OUT1 of the pre-output stage circuit, a source of the second NMOS transistor (M2) is an output port and constitutes one power equal division output end OUT3 of the error-controllable ultra-wideband compact active power divider, the source is further grounded through a fourth resistor R4, a drain of the second NMOS transistor (M2) is connected to a power source VDD through a third resistor R3, the drain is further grounded through one load balancing adjustable device, and the third resistor RL3 and the fourth resistor RL4 have the same resistance value.
  4. 4. The error-controllable ultra-wideband compact active power divider according to claim 1, characterized in that the second output stage circuit is as follows: a gate of the third NMOS transistor (M3) is connected to a second pre-output port OUT2 of the pre-output stage circuit, a drain of the third NMOS transistor (M3) is an output port and constitutes one power equal division output end OUT4 of the error-controllable ultra-wideband compact active power divider, the drain is further 1() connected to a power source VDD through a fifth resistor R5, a source of the third NMOS transistor (M3) is grounded through a sixth resistor R6, and the source is further grounded through one load balancing adjustable device, and the fifth resistor RL5 and the sixth resistor RL6 have the same resistance value.
  5. 5. The error-controllable ultra-wideband compact active power divider according to claim 1 or 3 or 4, characterized in that the load balancing adjustable device is an adjustable resistor (R).
  6. 6. The error-controllable ultra-wideband compact active power divider according to claim 1 or 3 or 4, characterized in that the load balancing adjustable device is an adjustable capacitor (C).
  7. 7. The error-controllable ultra-wideband compact active power divider according to claim 1 or 3 or 4, characterized in that the load balancing adjustable device is composed of an adjustable resistor (R) and an adjustable capacitor (C) connected in parallel.
  8. 8. The error-controllable ultra-wideband compact active power divider according to claim 1, characterized in that a first resistor RL1 and a second resistor RL2 with which a drain and a source of the first NMOS transistor (M1) are connected in series, a third resistor RL3 and a fourth resistor RL4 with which a drain and a source of the second NMOS transistor (M2) are connected in series, and a fifth resistor RL5 and a sixth resistor RL6 with which a drain and a source of the third NMOS transistor (M3) are connected in series, have the same resistance value.
GB2013539.8A 2019-09-24 2020-08-28 Error-controllable ultra-wideband compact active power divider Active GB2589951B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910907781.5A CN110739933B (en) 2019-09-24 2019-09-24 Error-controllable ultra-wideband compact active power distributor

Publications (3)

Publication Number Publication Date
GB202013539D0 GB202013539D0 (en) 2020-10-14
GB2589951A true GB2589951A (en) 2021-06-16
GB2589951B GB2589951B (en) 2023-04-19

Family

ID=69269475

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2013539.8A Active GB2589951B (en) 2019-09-24 2020-08-28 Error-controllable ultra-wideband compact active power divider

Country Status (2)

Country Link
CN (1) CN110739933B (en)
GB (1) GB2589951B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246003A (en) * 1987-04-01 1988-10-13 Tokyo Keiki Co Ltd High frequency power distributer
JPH06188611A (en) * 1992-12-22 1994-07-08 A T R Koudenpa Tsushin Kenkyusho:Kk Microwave signal distributing circuit
US20090243728A1 (en) * 2008-03-28 2009-10-01 Nec Electronics Corporation Splitter circuit
CN108599734A (en) * 2018-05-10 2018-09-28 南京信息工程大学 Broadband active power splitter and broadband active power combiner

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8188904B2 (en) * 2008-10-09 2012-05-29 Infineon Technologies Ag RF circuit with improved antenna matching
CN103887585B (en) * 2012-12-21 2017-02-08 上海联影医疗科技有限公司 3db bridge power divider
JP6219598B2 (en) * 2013-05-23 2017-10-25 新日本無線株式会社 High frequency power distributor
CN103746665B (en) * 2013-10-17 2017-01-25 天津大学 Drive power amplifier with adjustable gain of 0.1-3GHz CMOS

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246003A (en) * 1987-04-01 1988-10-13 Tokyo Keiki Co Ltd High frequency power distributer
JPH06188611A (en) * 1992-12-22 1994-07-08 A T R Koudenpa Tsushin Kenkyusho:Kk Microwave signal distributing circuit
US20090243728A1 (en) * 2008-03-28 2009-10-01 Nec Electronics Corporation Splitter circuit
CN108599734A (en) * 2018-05-10 2018-09-28 南京信息工程大学 Broadband active power splitter and broadband active power combiner

Also Published As

Publication number Publication date
GB2589951B (en) 2023-04-19
CN110739933A (en) 2020-01-31
CN110739933B (en) 2023-05-30
GB202013539D0 (en) 2020-10-14

Similar Documents

Publication Publication Date Title
US8482364B2 (en) Differential cross-coupled power combiner or divider
US11546012B2 (en) Signal processing device, amplifier, and method
US9634615B1 (en) Multi-band Doherty amplifier device and method therefor
Xia et al. Digitally-assisted 27-33 GHz reflection-type phase shifter with enhanced accuracy and low IL-variation
US10505247B2 (en) Circulator device with two magnet-free circulators
Park et al. A new compact CMOS distributed digital attenuator
US6806792B2 (en) Broadband, four-bit, MMIC phase shifter
Nam et al. A full X-band phased-array transmit/receive module chip in 65-nm CMOS technology
CN114514704A (en) Broadband transmitter for millimeter wave wireless communication
WO2007034658A1 (en) Balun circuit and integrated circuit apparatus
TW201947887A (en) Radio frequency frontend circuit for millimeter-wave 5G communication
GB2588510A (en) Power distribution unit circuit and power distribution structure for integrated transceiver system
WO2024026945A1 (en) Dual-frequency millimeter wave phased array system
Yu et al. A 60-GHz vector summing phase shifter with digital tunable current-splitting and current-reuse techniques in 90 nm CMOS
GB2589951A (en) Error-controllable ultra-wideband compact active power divider
Yu et al. Synthesis of filtering power divider with complex source and load impedances
US8275342B2 (en) Downconversion mixer
CN112019192B (en) High-order coupling quadrature signal generation circuit based on transformer and application thereof
US9966931B2 (en) Active quasi circulator
Yu et al. An 18$\sim $30 GHz Vector-Sum Phase Shifter With Two-Stage Transformer-Based Hybrid in 130-nm SiGe BiCMOS
Dilshad et al. An Ultra-Broadband K/Ka-Band (17–40 GHz) LNA MMIC in $0.15\mu\mathrm {m} $ GaAs pHEMT
Wang et al. A 25-31 GHz 6-bit switch-type phase shifter in 0.13 um SOI CMOS process for 5G mmWave phased array communications
Lv et al. A 14-18GHz 6bit passive phase shifter in 0.13 µm SiGe BiCMOS
Liu et al. High-order subharmonically pumped mixers using phased local oscillators
Li et al. Design of Ku-Band Bi-Directional Wideband Active Phase Shifter Using Reconfigurable Network