GB2588510A - Power distribution unit circuit and power distribution structure for integrated transceiver system - Google Patents
Power distribution unit circuit and power distribution structure for integrated transceiver system Download PDFInfo
- Publication number
- GB2588510A GB2588510A GB2013503.4A GB202013503A GB2588510A GB 2588510 A GB2588510 A GB 2588510A GB 202013503 A GB202013503 A GB 202013503A GB 2588510 A GB2588510 A GB 2588510A
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- GB
- United Kingdom
- Prior art keywords
- power distribution
- nmos transistor
- distribution unit
- source
- unit circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—DC amplifiers in which all stages are DC-coupled
- H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
- H03F3/347—DC amplifiers in which all stages are DC-coupled with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/36—Networks for connecting several sources or loads, working on the same frequency band, to a common load or source
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L5/00—Automatic control of voltage, current, or power
- H03L5/02—Automatic control of voltage, current, or power of power
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0413—MIMO systems
- H04B7/0426—Power distribution
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
- H03F2203/21106—An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Amplifiers (AREA)
Abstract
A power distribution unit circuit, i.e. an active power divider, comprises first, second and third NMOS transistors M1-M3, each having the same structure; the drain of each transistor is connected to a power source through a resistive load structure RD and the source of each transistor is grounded through a resistive load structure RS. The gate of the first transistor constitutes an input end of the distribution circuit and is connected to an input signal IN; the drain and source of the first transistor are respectively connected to the gates of the second and third transistors. The source of the second transistor and drain of the third transistor are each grounded through resistors R2, R3 and constitute output ends OUT1, OUT2 of the distribution circuit; the remaining drain and source connections of the second are third transistors are also grounded through balancing resistors R1, R4. A power distribution structure comprising N power distribution unit circuits is also provided, where each output of a distribution circuit is connected to an input of the next circuit (Fig.2). The power distribution circuit and structure may be used in an integrated transceiver system where small chip area is advantageous and equal division of signal power is required.
Description
POWER DISTRIBUTION UNIT CIRCUIT AND POWER DISTRIBUTION
STRUCTURE FOR INTEGRATED TRANSCEIVER SYSTEM
Technical field
The present invention relates to a power distribution structure. In particular, it relates to a power distribution unit circuit and a power distribution structure for an integrated transceiver system.
Technical background
With the development of wireless communication technology, frequency resources are becoming increasingly tight, and communication systems have begun to expand to higher frequency bands. Millimeter-wave frequency bands are rich in frequency resources. At the same time, increasing the frequency can also achieve higher transmission rates. However, as the frequency increases, the attenuation of electromagnetic waves in the propagation medium also increases. Therefore, multiple-input multiple-output (MIMO) antenna array technology is generally required to increase the output power of the communication system.
In a MIMO system, the signal power needs to be equally distributed among multiple channels. A current common structure for achieving this power distribution is a Wilkinson power distribution structure. The main disadvantages of this structure include the inherent loss of 3dB per stage of power allocation caused by equal division of power and the large chip area that is difficult to compress. Therefore, this structure is very uneconomical. In addition, some systems also use a structure combining the Wilkinson structure with a power amplifier. This structure can reduce the loss and reduce the area to a certain extent, but the compression effect on the area is not significant. Therefore, a compact and low-loss power distribution scheme is desirable to help greatly reduce system costs and facilitate large-scale array applications with integrated transceiver systems.
Summary of the invention
A technical problem to be solved by the present invention is to provide a power distribution unit circuit and a power distribution structure for an integrated transceiver system, which can achieve multi-channel equal division of signal power while occupying a small chip area.
A technical solution adopted by the present invention is: a power distribution unit circuit, comprising a first NMOS transistor, a second NMOS transistor and a third NMOS transistor having the same structure, wherein the first NMOS transistor, the second NMOS transistor and the third NMOS transistor each have a drain connected to a power source through a drain resistive load structure, and each have a source grounded through a source resistive load structure; a gate of the first NMOS transistor constitutes an input end of the power distribution unit circuit connected to an externally input signal IN, the drain is connected to a gate of the second NMOS transistor, and the source is connected to a gate of the third NMOS transistor; the drain of the second NMOS transistor is grounded through a first balancing resistor, the source constitutes an output end OUT1 of the power distribution unit circuit, and the source is further grounded through a first resistor; and the source of the third NMOS transistor is grounded through a second balancing resistor, the drain constitutes another output end OUT2 of the power distribution unit circuit, and the drain is further grounded through a second resistor.
The first balancing resistor and the second balancing resistor both have a resistance value of 50 ohms.
Output signal gains Avi and Av2 of the output ends OUT1 and OUT2 of the power distribution unit circuit are as follows: A\-1 (1) where gm is transconductance of each NMOS transistor, and R is the resistance value of the drain resistive load structure or source resistive load structure connected in series with the drain or the source of each NMOS transistor.
A power distribution structure for an integrated transceiver system composed of the power distribution unit circuit, comprising N power distribution unit circuits, wherein each power distribution unit circuit has one input end and two output ends, the input end of a first power distribution unit circuit is connected to an external input signal IN, and the two output ends of each power distribution unit circuit are separately connected to the input end of one power distribution unit circuit to together form the power distribution structure for the integrated transceiver system with 211 same outputs.
The power distribution unit circuit and the power distribution structure for the integrated transceiver system of the present invention can achieve multi-channel equal division of signal power in a case of occupying a small chip area. The beneficial effects of the present Invention are as follows: (1) The active structure is used to achieve power distribution, which avoids the inherent loss of 3dB per stage due to equal division of power. The operating mode of an amplifier composed of transistors not only compensates for the loss, but also brings a certain gain.
(2) The power distribution structure with the active structure as the main body greatly alleviates the chip area problem caused by large-area passive devices and reduces the chip cost.
(3) The unit circuit structure composed of three NMOS transistors theoretically achieves the two output ends with strictly the same power magnitude and the consistent phase, and the power distribution error is small.
(4) The proposed power distribution unit circuit is easy to cascade in multiple stages, and the multi-stage connection of the unit circuits can be realized by means of simple coupling, thereby realizing large-scale multi-channel power distribution.
Brief description of the drawings
Fig. 1 is a schematic diagram of configuration of a power distribution unit circuit of the present invention.
Fig. 2 is a block diagram of circuit configuration of a power distribution structure for an integrated transceiver system of the present invention.
Detailed description of the embodiments
A power distribution unit circuit and a power distribution structure for an integrated transceiver system of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
In the power distribution unit circuit of the present invention, in a CMOS process, a basic unit circuit structure is composed of three exactly identical NMOS (N-Metal-Oxide-Semiconductor) transistors, wherein one transistor uses a dual-output mode of a source output and a drain output, and the other two transistors use a drain output mode and a source output mode.
As shown in Fig. 1, the power distribution unit circuit of the present invention includes a first NMOS transistor Ml, a second NMOS transistor M2 and a third NMOS transistor M3 having the same structure. The first NMOS transistor Ml, the second NMOS transistor M2 and the third NMOS transistor M3 each have a drain connected to a power source through a drain resistive load structure RD, and each have a source grounded through a source resistive load structure Rs. A gate of the first NMOS transistor M1 constitutes an input end of the power distribution unit circuit connected to an externally input signal IN, the drain is connected to a gate of the second NMOS transistor M2, and the source is connected to a gate of the third NMOS transistor M3. The drain of the second NMOS transistor M2 is grounded through a first balancing resistor R1, the source constitutes an output end OUT1 of the power distribution unit circuit, and the source is further grounded through a first resistor R2. The source of the third NMOS transistor M3 is grounded through a second balancing resistor R4, the drain constitutes another output end OUT2 of the power distribution unit circuit, and the drain is further grounded through a second resistor R3.
The first balancing resistor R1 and the second balancing resistor R4 both have a resistance value of 50 ohms.
Output signal gains Avi and Av2 of the output ends OUT1 and OUT2 of the power distribution unit circuit of the present invention are as follows: (1) where gm is transconductance of each NMOS transistor, and R is the resistance value of the drain resistive load structure or source resistive load structure connected in series with the drain or the source of each NMOS transistor.
The power distribution unit circuit of the present invention provides two output ports that can achieve equal division of power of one input signal. Finally, the signals output from the two ports have the same power magnitude and the consistent phase within a certain error range.
As shown in Fig. 2, a power distribution structure for an integrated transceiver system composed of the power distribution unit circuit of the present invention includes N power distribution unit circuits A. Each power distribution unit circuit A has one input end and two output ends, the input end of a first power distribution unit circuit A is connected to an external input signal IN, and the two output ends of each power distribution unit circuit A are separately connected to the input end of one power distribution unit circuit A, to together form a power distribution structure for an integrated transceiver system with 2" same outputs.
The power distribution unit circuit of the present invention can be used for large-scale power distribution in a transceiver system only by means of simple coupling. It can realize the power distribution function of 1: 2. On this basis, it continues to cascade and can realize the power distribution structure of 1: 4, 1: 8, ..., and 1: N in sequence. Since the main body in the power distribution structure is composed of active devices, and a very small number of passive devices are included, a large value of N can be achieved with a smaller chip area.
Claims (4)
- Claims 1. A power distribution unit circuit, characterized in that it comprises a first NMOS transistor (M1), a second NMOS transistor (M2) and a third NMOS transistor (M3) having the same structure, wherein the first NMOS transistor (M1), the second NMOS transistor (M2) and the third NMOS transistor (M3) each have a drain connected to a power source through a drain resistive load structure (RD), and each have a source grounded through a source resistive load structure (Rs); a gate of the first NMOS transistor (M1) constitutes an input end of the power distribution unit circuit connected to an externally input signal IN, the drain is connected to a gate of the second NMOS transistor (M2), and the source is connected to a gate of the third NMOS transistor (M3); the drain of the second NMOS transistor (M2) is grounded through a first balancing resistor (R1), the source constitutes an output end OUT1 of the power distribution unit circuit, and the source is further grounded through a first resistor (R2); and the source of the third NMOS transistor (M3) is grounded through a second balancing resistor (R4), the drain constitutes another output end 0U12 of the power distribution unit circuit, and the drain is further grounded through a second resistor (R3).
- 2. A large-scale power distribution structure for an integrated transceiver system according to claim 1, characterized in that the first balancing resistor (R1) and the second balancing resistor (R4) both have a resistance value of 50 ohms.
- 3. A large-scale power distribution structure for an integrated transceiver system according to claim 1, characterized in that output signal gains Avi and Avs of the output ends OUT1 and 0U12 of the power distribution unit circuit are as follows: (1) where gm is transconductance of each NMOS transistor, and R is the resistance value of the drain resistive load structure or source resistive load structure connected in series with the drain or the source of each NMOS transistor.
- 4. A power distribution structure for an integrated transceiver system composed of the power distribution unit circuit of claim 1, characterized in that it comprises N power distribution unit circuits (A), wherein each power distribution unit circuit (A) has one input end and two output ends, the input end of a first power distribution unit circuit (A) is connected to an external input signal IN, and the two output ends of each power distribution unit circuit (A) are separately connected to the input end of one power distribution unit circuit (A), to together form a power distribution structure for an integrated transceiver system with 2" same outputs.S
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910907320.8A CN110535502B (en) | 2019-09-24 | 2019-09-24 | Power distribution unit circuit and power distribution structure for integrated transceiver system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB202013503D0 GB202013503D0 (en) | 2020-10-14 |
| GB2588510A true GB2588510A (en) | 2021-04-28 |
| GB2588510B GB2588510B (en) | 2021-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2013503.4A Active GB2588510B (en) | 2019-09-24 | 2020-08-28 | Power distribution unit circuit and power distribution structure for integrated transceiver system |
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| Country | Link |
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| CN (1) | CN110535502B (en) |
| GB (1) | GB2588510B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113630262B (en) * | 2021-07-28 | 2023-12-15 | 常州瑞思杰尔电子科技有限公司 | Multiunit homophase 100W60MHz radio frequency power supply system |
| CN117039459B (en) * | 2023-10-09 | 2023-12-12 | 成都智芯雷通微系统技术有限公司 | High-integration-level T/R assembly for millimeter wave active phased array |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06188611A (en) * | 1992-12-22 | 1994-07-08 | A T R Koudenpa Tsushin Kenkyusho:Kk | Microwave signal distributing circuit |
| US20090243728A1 (en) * | 2008-03-28 | 2009-10-01 | Nec Electronics Corporation | Splitter circuit |
| CN108599734A (en) * | 2018-05-10 | 2018-09-28 | 南京信息工程大学 | Broadband active power splitter and broadband active power combiner |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3758545B2 (en) * | 2001-10-03 | 2006-03-22 | 日本電気株式会社 | Sampling level conversion circuit, two-phase and multiphase expansion circuit, and display device |
| JP6171311B2 (en) * | 2012-11-12 | 2017-08-02 | 住友電気工業株式会社 | Differential amplifier circuit |
| CN104917466B (en) * | 2015-06-11 | 2017-08-11 | 东南大学 | A kind of pulse power amplifier of use drain modulation mode |
| US10153739B2 (en) * | 2017-03-21 | 2018-12-11 | Panasonic Corporation | Power amplification division circuit and multi-stage type power amplification division circuit |
| US10686258B2 (en) * | 2017-09-18 | 2020-06-16 | Integrated Device Technology, Inc. | Hard-wired address for phased array antenna panels |
| CN207442799U (en) * | 2017-12-05 | 2018-06-01 | 成都镓谷半导体有限公司 | A kind of GaAs multi-channel power synthesis amplifier |
-
2019
- 2019-09-24 CN CN201910907320.8A patent/CN110535502B/en active Active
-
2020
- 2020-08-28 GB GB2013503.4A patent/GB2588510B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06188611A (en) * | 1992-12-22 | 1994-07-08 | A T R Koudenpa Tsushin Kenkyusho:Kk | Microwave signal distributing circuit |
| US20090243728A1 (en) * | 2008-03-28 | 2009-10-01 | Nec Electronics Corporation | Splitter circuit |
| CN108599734A (en) * | 2018-05-10 | 2018-09-28 | 南京信息工程大学 | Broadband active power splitter and broadband active power combiner |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110535502A (en) | 2019-12-03 |
| CN110535502B (en) | 2021-05-28 |
| GB2588510B (en) | 2021-10-20 |
| GB202013503D0 (en) | 2020-10-14 |
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